- Free
- Hackable
- Powerful
As a result of this I have started working on my own software for this purpose, I am planning to make it have at least these features:
- Timing analysis
- Data level signal inspection ( grouping buses and showing the actual value instead of 2^N high/low values )
- Netlist export
- Eurocard layout editor
- Schematic entry
The project is written in Java, as it is an easy language for application development.
GitHub Project: https://github.com/peterbjornx/openlogiceda
Progress:
January 9, 2017 - First Simulator tests
A circuit with two clocks and an AND gate: ( notice the propagation delay ):
January 12, 2017 - Working on the component symbol editor
Testing pin placement,
Functions already implemented: Undo/Redo, Copy, Delete, Move, Rotate, Add, Context menu, Select, Multiple select, Save, Open, Edit properties