Meaty Skeleton - No rule to make target

[bilsch01]

I'm adding a GAS assembler file named kb1.S in Meaty Skeleton that gets keyboard input. There is already a GAS file in the build named boot.S and the only rule for that one is:

Code: Select all

%.o: %.S
	$(CC) -c $< -o $@ $(CFLAGS) $(CPPFLAGS)

When I run Make I get the message: No rule to make target (ARCHDIR)/kb1.o.
Why isn't the existing rule sufficient for the added GAS file kb1.S ? What can I do?

A variable in an included makefile (make.config) has the object files from both GAS files:

Code: Select all

KERNEL_ARCH_OBJS:=\
$(ARCHDIR)/boot.o \
$(ARCHDIR)/tty.o \
(ARCHDIR)/kb1.o \

[Combuster]

Have you looked carefully? What's the letter-by-letter difference between the boot.o line and the kb1.o line in your make.config?

[bilsch01]

Have you looked carefully? What's the letter-by-letter difference between the boot.o line and the kb1.o line in your make.config?

Okay. Got it. Thanks. Bill S.

[glauxosdever]

Hi,

There is already a GAS file in the build named boot.S and the only rule for that one is:

Code: Select all

%.o: %.S
	$(CC) -c $< -o $@ $(CFLAGS) $(CPPFLAGS)

This seems suspiciously wrong. Are you really trying to assemble an assembly file with GCC?

Hint: $(CC) stands for C Compiler, what you want is $(AS).


Regards,
glauxosdever

[mikegonta]

There is already a GAS file in the build named boot.S and the only rule for that one is:

Code: Select all

%.o: %.S
	$(CC) -c $< -o $@ $(CFLAGS) $(CPPFLAGS)

This seems suspiciously wrong. Are you really trying to assemble an assembly file with GCC?
Hint: $(CC) stands for C Compiler, what you want is $(AS).

GCC will be more then happy to assemble the .S file to an object file (.o).
In fact it will first pass it to cpp the C preprocessor and then pass it along to AS.

PS. Bill has been keeping us entertained here and here.

[glauxosdever]

Hi,

GCC will be more then happy to assemble the .S file to an object file (.o).
In fact it will first pass it to cpp the C preprocessor and then pass it along to AS.

I'm not sure it is a portable solution. You can't assume every C compiler will actually assemble assembly code.

PS. Bill has been keeping us entertained here and here.

I don't see the point of this statement.


Regards,
glauxosdever

[Solar]

I'm not sure it is a portable solution. You can't assume every C compiler will actually assemble assembly code.

Err... can you assumbe that any two assemblers would actually assemble your source code?

Anyway, GNU make implicit rules actually use $(CC) to turn .s into object code if you link directly (i.e. omit the -c), so it's not as if using $(CC) for assembly is something the OP came up with... but yes, on the other hand GNU make uses $(AS) for implicitly turning .s to intermediate .o, so both of you have a point.