DMA

[icealys]

when the cpu gives an address to the DMA controller to write to, is it a physical address or virtual?

[Combuster]

Where is virtual memory implemented?
Is the DMA controller part of that?

[icealys]

virtual memory is implemented on the operating system...the OS maps virtual addresses to physical addresses and updates a page table which is sent to the memory management unit. With DMA, the cpu initiates the transfer by sending the number of bytes and the write address to the dma controller. It allows the cpu to do other operations while I/O from a device is in progress. My question is...is the dma controller aware of virtual addresses? Or just physical addresses?

[thepowersgang]

Would it make sense to apply a mapping that could change when a process switch hapens (which could be at any time) to an asynchronous hardware device? Answer that and you have the answer to your original question.

[Combuster]

the OS maps virtual addresses to physical addresses and updates a page table which is sent to the memory management unit.

Now again, what is actually performing virtual to physical translations? How is it wired to the DMA controller?

[icealys]

Now again, what is actually performing virtual to physical translations? How is it wired to the DMA controller?

the MMU is doing the translations and I think anytime you access RAM the transfer needs to go through the MMU.

thepowersgang: what do you mean by applying mapping to an asynchronous hardware device? Do you mean to tell me that the mmu gets updated and knows what the current running process is?

[Combuster]

I think

Wrong. Don't think, know. If you only think it means you're too lazy to make sure.

Now back to the original question: Where is the MMU implemented? Where is the DMA controller?

[icealys]

Now back to the original question: Where is the MMU implemented? Where is the DMA controller?

umm I'm not too sure why you are asking these questions in my thread but they are both on the die of the cpu.

[Combuster]

umm I'm not too sure why you are asking these questions in my thread

Because I want to teach you something more important than just the answer, and the alternative is reporting you for breaking forum rules (smart questions, required knowledge).

but they are both on the die of the cpu.

Post your source, please.

[mathematician]

Now back to the original question: Where is the MMU implemented? Where is the DMA controller?

umm I'm not too sure why you are asking these questions in my thread but they are both on the die of the cpu.

The DMA controller is in the South Bridge. Hisorically it was a self contained chip.

virtual memory is implemented on the operating system...

Virtual memory is implemented in the processor, and the operating system makes use of the hardware's capabilities. Just as it does with the DMA controller.

[icealys]

thats true...

the IOMMU is what makes it possible for DMA to use virtual addresses which hides fragmentation of physical RAM.

[mathematician]

thats true...

the IOMMU is what makes it possible for DMA to use virtual addresses which hides fragmentation of physical RAM.

DMA doesn't use virtual addresses. The chipset knows nothing about the memory mapping effected by the CPU. It uses physical addresses. That is why the OS's memory manager has to make special arrangements for devices which need contiguous chunks of physical memory.

[icealys]

thx for clearing that up...but what is the IOMMU used for then?

[Combuster]

The DMA controller is in the South Bridge. Hisorically it was a self contained chip.

Thanks for providing the incomplete answer. Actually, there are many DMA controllers in a computer - none of which are in the CPU because DMA is meant to bypass the CPU.
But yes, ISA DMA is typically on the southbridge.

DMA doesn't use virtual addresses.

Not exactly true. It does if there's a GART or IOMMU in the way.

IOMMU

Which is not the MMU, is located elsewhere (not on the CPU), but still performs the same task of address translation and protection. Although more often than that, it's not even present at all.

When it does exist, it acts completely independent from the CPU, and needs to be configured explicitly to do something other than pretending it doesn't exist.