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Main idea is very simple:
Author of that topic added bootable image that demonstrates the problem: http://osdev.ru/download/file.php?id=29 , if this link is broken, you can use my one: ftp://93.175.16.134/boot.zipLAPIC timer divisior is updated only when counter wraps but bare hardware and other VMs update it on the fly
My translation of test description:
1. PIT is clocked to 50Hz, LAPIC timer - 10 kHz (divisor is 16), i.e. there are 200 APIC timer ticks between 2 PIT ticks.
2. Kernel counts APIC timer interrupts during one period of PIT, then changes divisor to 8 and counts APIC ticks during one period.
3. Then test reloads TICR with the value from p.1 and counts ticks again.
4. Then it disables both timers and display result.
On bare hardware and under virtualbox we have smth about 200/400/400 but under bochs 200/200/400 ticks.