why no memory barriers on example code ?

[cds84]

Hi guys... Just a quick question.
Ive noticed the lack of any memory barriers in some of the wiki code snippets.

Have I completely misunderstood out-of-order execution ?

for example, take the following code snipped from the IO-APIC wiki page.

Code: Select all

 void write_ioapic_register(const ptr_t apic_base, const uint8_t offset, const uint32_t val)
 {
     /* tell IOREGSEL where we want to write to */
     *(uint32_t*)(apic_base) = offset;
     /* write the value to IOWIN */
     *(uint32_t*)(apic_base + 0x10) = val;
 }

Don't we need an sfence between the two writes, to make sure the value doesn't get written before the register is selected ?

Surely the out of order execution engine isn't clever enough to see the virtual address writes are mapped to the IOAPIC ?

Thanks.

[Owen]

No. Intel and AMD both have very good descriptions of the x86 memory ordering model. It can be summed up as, on a single CPU, being that all operations will (appear to) complete before any following operations. In a multicore setup, it is guaranteed that, if you observe the result of an operation on another core, then (from your point of view) all preceding operations on that core will have completed.

[gerryg400]

The compiler, on the other hand might re-order things so you need to cast the the register addresses to pointers-to-volatile.