* "Standard" 32-bit paging: PageDirectoy => PageTable => Frame. PD and PT with 1024 entries each.
* PAE paging: PDPT => PageDirectory => PageTable => Frame. PDPT with 4 entries, PD and PT with 512 entries.
* Long mode (IA-32e) paging: PML4 => PDPT => PageDirectory => PageTable => Frame. All structures made of 512 entries.
Now. I tought at first that it would have been nice to create two kernels as many do here:
* A kernel for quite outdated machines (x86 archs)
* A kernel to use all the potential of your pc and run at full speed (x86_64)
I tought to implement both standard paging and pae paging into the x86 version and only the IA-32e paging in the x86_64 one (which is required).
It is easy to go from PAE to IA-32e: just add a new structure (PML4) and make the PDPT containing 512 entries instead of just 4. Set some flags and it's all right. But the transistion from 32-bit paging and PAE is not so obvious. It's not matter of adding another structure. You basically need this (eg):
Code: Select all
struct PageTable
{
uintptr_t frames[NumberOfEntries];
}
Since I wouldn't like to plan triple-version (x86 no PAE, x86 PAE, x86_64) releases, here's my question: is it fair to expect PAE to be present on the system?
PAE was introduced in 1995 by Intel with the Pentium Pro, and it's available on all of them processors since then (P2, P3, P4, all cores and Celerons) with the only exception of the Pentium M at 400 Mhz. It has been supported by AMD since 1999 with the Athlon K7. So you would only get stuck on an old AMD K6 (which, twist of fate, I own), or pre-PentiumPro CPUs. How many use such a processor at home? Or at work? Are them still so widely used?
Thanks