Positive/subtractive decode....

[A5]

Hi!
Can anyone help me a bit to understand what this terms are?
I am now reading the PCI-ISA spec for my machine and this two terms appears often.

[JamesM]

Hi,

Could you please post the context in which they are used? The paragraph will do.

Cheers,

James

[A5]

Just as an example:

For PCI accesses to ISA memory, accesses below 16 Mbytes (including BIOS space) that are not claimed by
a PCI device are forwarded to ISA when subtractive decode is enabled. If subtractive decode is disabled,
PIIX4 forwards cycles for programmable ranges (32 KB–4 MB) associated with power management devices
12 and 13 and for BIOS ranges described below.

[Mohanty]

ISA=Industry Standard Architecture bus
PCI=Peripheral Component Interconnect bus

These are 2 different Bus. That means u r reading about buses spec......
By the way which purpose u r reading them now............

PCI is a computer bus used for attaching peripheral devices to a computer motherboard. It is the most popular local I/O bus. PCI devices are plug and play devices.
http://www.tech-faq.com/pci.html

Plug and Play ISA enables the operating system to configure expansion boards automatically so that users do not need to fiddle with DIP switches and jumpers.

[A5]

From the net:

The method normally used to handle transactions destined for an ISA expansion bus is to use a process of subtractive decoding, or "if nobody else wants it, it must be for me." The expansion bus bridge claims the transaction if it is for a memory address in the first 16MB of address space or an I/O port address in the first 64KB, and no PCI device has claimed the transaction within a set delay period. The delay period depends on the speed of the PCI device address decoders, which can take from one to three clock cycles to respond with an acknowledgeme

Now I have another question: In the part of one of the Power management modes, the spec talks about L2 cache powering to preserve data.

Will the cache L1 lose its data on CPU power down/restart and L2 too if not powered/refreshed like the RAM? Cache functionality is supposed to be almost transparent to software, do I have to consider this cache behavior when OS resume from suspend states?

[bewing]

One of the saddest things about specsheets is that more than half of almost any spec is targeted at hardware designers ONLY, and has no bearing on software drivers at all. In this case, I am pretty certain that the answer is no, this is something that is handled exclusively in hardware, per the spec.

[A5]

I observed the same thing. Personally I can(am capable to) use only a little part of the spec info.