Looking for an Ada or C/C++ programmer

[earlz]

Wow, I almost missed it.. Thanks for telling me so I could grab a screeny.

Have you considered like the Core(I think thats the name) processor? Like the processors used in the Playstation 3? Where they are massively parallel and vectorized? Would vectorization be better for sound? I would think so.

Also I think in order to stay hardware independent, you would have to write a microkernel-ish design. Like you have a small core kernel and then you have linked in(probably static for speed) modules for interfacing with the hardware specific portions.

[kameo76890]

Have you considered like the Core(I think thats the name) processor? Like the processors used in the Playstation 3? Where they are massively parallel and vectorized? Would vectorization be better for sound? I would think so.

It's not the Core, the CellBE is what's used in the PS3, SPURS Engine, and some of IBM's and Mercuries servers. -- CellBE: Cell Broadband Engine - http://www.ibm.com/developerworks/power/cell/

The CellBE's main focus is double-precision floating point calculations, which is what the CellBE's SPE's are all about. Audio doesn't need floating points, so it doesn't really benefit from the main point of the CellBE, basically you get the same performance as a comparable POWER. -- SPE: Synergistic Processing Element.

Also I think in order to stay hardware independent, you would have to write a microkernel-ish design. Like you have a small core kernel and then you have linked in(probably static for speed) modules for interfacing with the hardware specific portions.

I know what a microkernel is
Yes, most of my designs have been microkernels, extreme microkernels. For a project like this, the only parts that should be in kernel space, are those which have to be in kernel space, and certain audio parts, because the latency from moving out into user space can become destructive. This is one of the few situations in which it's pointless for it to be self healing, because if you've got a hiccup, you basically have to scrap the whole section of audio anyways.

Well I think by now it's pretty clear this isn't a "next windows" vapor-project...
I've got most of the theoretics and general design already done, I'm mostly looking for someone to join in on the fun of actually doing it up.

[quok]

Wow, I almost missed it.. Thanks for telling me so I could grab a screeny.

Have you considered like the Core(I think thats the name) processor? Like the processors used in the Playstation 3?

That would be the Cell processor. It's based on the Power architecture. Each Cell processor has 2 cores, an AltiVec unit, and 8 SPEs (Synergistic Processing Elements) which are basically 128-bit SIMD RISC processors.

Next time, a quick google to make sure you're giving the correct information would be nice.

Edit: Bah, kameo76890 beat me to it.

[earlz]

@quok:
Yea, I should've did a wikipedia test or something to make sure.. but anyway

Well I think by now it's pretty clear this isn't a "next windows" vapor-project...
I've got most of the theoretics and general design already done, I'm mostly looking for someone to join in on the fun of actually doing it up.

I'm always interested in more ambitious projects.. but this one I don't think I could help with like at all lol. I know low level programming C, but not anything about the requirements of RTOSs and DSPs and all of that and how to manage cross-platform stuff for such a wide range of hardware

[kameo76890]

That would be the Cell processor. It's based on the Power architecture. Each Cell processor has 2 cores, an AltiVec unit, and 8 SPEs (Synergistic Processing Elements) which are basically 128-bit SIMD RISC processors.

To be correct, the central part of the CellBE is just a POWER chip, I beleive it was the POWER 6 although I'm not positive on that. Technically speaking the CellBE has 10 cores, but 8 of them are rather simplistic, and can't do anything other than co-processing).

[quok]

That would be the Cell processor. It's based on the Power architecture. Each Cell processor has 2 cores, an AltiVec unit, and 8 SPEs (Synergistic Processing Elements) which are basically 128-bit SIMD RISC processors.

To be correct, the central part of the CellBE is just a POWER chip, I beleive it was the POWER 6 although I'm not positive on that. Technically speaking the CellBE has 10 cores, but 8 of them are rather simplistic, and can't do anything other than co-processing).

Since you wanted to nitpick, Cell is the more common name for the Cell Broadband Engine (CellBE). The PPE of Cell is "Power Architecture". The Power Architecture encompasses the POWER, PowerPC, and Cell processor lines. To make this even more confusing, the Power Architecture implements the PowerPC ISA.

POWER use to refer to the POWER ISA and the POWER cpus. These days, POWER refers to the processor series from IBM. POWER1 and POWER2 implemented the POWER ISA (which has since been dropped). Since POWER3, the POWER series uses the PowerPC ISA (and extensions implemented in new POWER cpus usually result in a new version of the PowerPC ISA).

The PPE used in Cell is neither POWER nor PowerPC. The PPE implements the PowerPC ISA. It is 64-bit, single core, and has 2 threads of execution ala SMT. There are 8 SPEs (each is single core and single threaded). That's a total of 9 cores. The Altivec unit is part of the PowerPC ISA since v2.03, which is what the Cell implements. It does not count as a separate core (in much the same way that the FPU on an x86 cpu doesn't count as a separate core).

In the PS3, one SPE is disabled and one is reserved for the OS, leaving 6 SPEs available to software. In servers and Cell co-processor cards, all the SPEs are enabled and available to all software.

[kameo76890]

Since you wanted to nitpick, Cell is the more common name for the Cell Broadband Engine (CellBE). The PPE of Cell is "Power Architecture". The Power Architecture encompasses the POWER, PowerPC, and Cell processor lines. To make this even more confusing, the Power Architecture implements the PowerPC ISA.

POWER use to refer to the POWER ISA and the POWER cpus. These days, POWER refers to the processor series from IBM. POWER1 and POWER2 implemented the POWER ISA (which has since been dropped). Since POWER3, the POWER series uses the PowerPC ISA (and extensions implemented in new POWER cpus usually result in a new version of the PowerPC ISA).

- Cell may be the more common name, but it's creators do refer to it as the CellBE, or CBEA.
-The Power Architecture encompasses the Power, PowerPC, POWER, PowerQUICC, QorIQ, CellBE and SpursEngine. Don't forget to mention the Power, it's not the same as the POWER.

The PPE used in Cell is neither POWER nor PowerPC. The PPE implements the PowerPC ISA. It is 64-bit, single core, and has 2 threads of execution ala SMT. There are 8 SPEs (each is single core and single threaded). That's a total of 9 cores. The Altivec unit is part of the PowerPC ISA since v2.03, which is what the Cell implements. It does not count as a separate core (in much the same way that the FPU on an x86 cpu doesn't count as a separate core).

In the PS3, one SPE is disabled and one is reserved for the OS, leaving 6 SPEs available to software. In servers and Cell co-processor cards, all the SPEs are enabled and available to all software.

• One or more PPEs

The Cell Broadband Engine Architecture (CBEA) includes PowerPC processors known as PowerPC
Processor Elements (PPEs).

- Not all CellBE based co-processors have all the SPE's, an example would be the SpursEngine used by Toshiba.

I suggest you read the "Introduction to Cell Broadband Engine Architecture" before lecturing me on the CellBE, it can be found at https://www-01.ibm.com/chips/techlib/te ... 6&S_CMP=LP

[earlz]

I'm thinking both of you need to quit nitpicking at small irrelevant details

[Combuster]

I'm thinking both of you need to quit nitpicking at small irrelevant details

+1

Not to mention that all this is deterring people from your project (Even though the probability of that happening was neglegible already)