Is address space common between cores in multicore proc

[sawdust]

Hi,
Is address space common between cores in multicore processor? E.g. if a physical address is mapped to a virtual address 0xabcdefabcedf, in a BSP, is it the same for the AP (running some guest OS) also?
TIA

[Brendan]

Hi,

Is address space common between cores in multicore processor? E.g. if a physical address is mapped to a virtual address 0xabcdefabcedf, in a BSP, is it the same for the AP (running some guest OS) also?

For all forms of multi-CPU (separate chips, multi-core and hyper-threading), every logical CPU has it's own CR3 which tells the logical CPU which virtual address space it's currently using. This means that every logical CPU can have it's own entirely separate virtual address space, or they can share virtual address spaces if you want.


Cheers,

Brendan

[Love4Boobies]

It depends on what type of system you're playing with. The two main types of MP systems are NUMA and SMP. In SMP, you have multiple CPUs using the same memory, in NUMA you may have multiple SMPs (1 or more CPUs), each with its own memory. Core i7 is the only Intel processor (and perhaps the only anyway) that combines both SMP and NUMA - you can use it however you want.

[Combuster]

NUMA is orthogonal to SMP - you can have both SMP systems with NUMA (the physical address spaces are the same for each execution unit, but not the route to each subsection of the address space), and you can have non-SMP NUMA systems (i.e. the megadrive console's main and audio processor have the system memory mapped at different locations in their address spaces)
Think about there being two computers (or one for each core) with a communication wire between them - if the wire is transparent to application programmers then its SMP, if you have to explicitly deal with it, its not.
If that wire slows down communication between each half, then its NUMA.

I haven't read up on i7, but it appears to me it is an uniform SMP system (Can't imagine intel to have each core a different interface to the memory controller)

[sawdust]

I'll try to be more specific. The machine has a dual-core AMD cpu and 2GiB RAM. Linux is on one core and a guest on another. They don't share any process. While linux does a 4KB paging, can the guest OS do a 2MB paging of the same memory?
TIA

[bewing]

As Brendan said, paging involves the virtual memory mappngs, and each core is completely independent.

[Love4Boobies]

i7 is both SMP and NUMA.

[Combuster]

i7 is both SMP and NUMA.

Explain why its NUMA?

[Owen]

Because i7 uses "Quick path interconnect" to the chipset and has an internal memory controller.

Yes, Intel are shamelessly copying AMD. Though why they don't just use HyperTransport is beyond me - it's an open (non AMD controlled) standard. Probably just to stop people using Intel CPUs and AMD chipsets (or vise versa)

[Combuster]

Having a memory controller on-die or not just makes a difference in where the wires are running, quickpath is only a different communication bus to the chipset.

That still doesn't make it NUMA because the access times to a certain memory unit are still the same for each processor core.

[Brendan]

Hi,

That still doesn't make it NUMA because the access times to a certain memory unit are still the same for each processor core.

It's "ccNUMA", the same as AMD's hyper-transport.

Code: Select all

RAM3 <--> Chip3 <--> Chip2 <--> RAM2
            |          |
            |          |
RAM1 <--> Chip1 <--> Chip0 <--> RAM0
                       |
                     IO_Hub

Of course we won't see any NUMA characteristics until next year, because Intel haven't released chips for "multi-chip" configurations yet (and there's no 2-way, 4-way or 8-way motherboards yet either).


Cheers,

Brendan