P.S. I read Solar's Makefile tutorial and well, there wasn't much I understood in there!
Perhaps we could work together - you pointing out what you did not understand, and me improving the tutorial?
The idea to have a script working around lacks of understanding of Makefile syntax is understandable, but if I were you, I'd try to
understand rather than
work around. What you wrote a script for, 'make' can do itself!
Getting all *.c files in a list:
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SOURCES := $(shell find . -name "*.c")
Getting the corresponding *.o filenames:
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OBJECTS := $(patsubst %.c,%.o,$(SOURCES))
And if the current directory's name is good enough for you as executable name, that can be done too:
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EXECUTABLE := $(notdir $(shell pwd))
If you want to get the commands explained ($shell, $patsubst, $notdir), they're in 'info make'.
A number of other flaws of your Makefile:
- Use := instead of =, so the commands get executed once, instead of everytime the variable is used.
- $(CC) is the C compiler. If you want the C++ compiler, use $(CXX) (and $(CXXFLAGS). Then you might want to find *.cpp files instead of *.c ones, too...
- -c should be part of the rule, not part of CFLAGS.
- Your 'all' rule does too much.
- Your "clean" rule would delete any file ending in o, not only *.o...
Your original Makefile, including my suggestions and the dependency handling from the tutorial, assuming C compilation:
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CFLAGS := -Wall -Wextra -pedantic -Wshadow -Wpointer-arith -Wcast-align \
-Wwrite-strings -Wmissing-prototypes -Wmissing-declarations \
-Wredundant-decls -Wnested-externs -Winline -Wno-long-long \
-Wconversion -Wstrict-prototypes
LDFLAGS :=
SOURCES := $(shell find . -name "*.c")
OBJECTS := $(patsubst %.c,%.o,$(SOURCES))
DEPENDENCIES := $(patsubst %.c,%.d,$(SOURCES))
EXECUTABLE := $(notdir $(shell pwd))
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $@
-include $(DEPENDENCIES)
%.o: %.cpp
$(CC) $(CFLAGS) -MMD -MP -MT "$*.d" -c $< -o $@
clean:
rm -rf *.o $(EXECUTABLE)
Not tested on your source tree, no guarantees given.