Hi,
neon wrote:Please let me know what you think, if you have any suggestions, comments, questions, or have any more information you would like to add.
I had a quick look (it looks good) - some notes...
1) You probably should mention local APICs and I/O APICs (even if all you do is say that they exist and aren't covered in the tutorial).
2) It'd be good to mention the PIC chip's spurious interrupt, why it's there and how an OS is meant to detect them and handle them.
3) In a few places you say "the processor has it's own internal PIC Microcontroller". AFAIK this is entirely wrong for 80x86 (even for modern AMD CPUs that have inbuilt memory controllers), and the PIC chips are built into the "PCI to LPC bridge" (or the chipset's southbridge). I'm wondering if you were thinking about the local APICs (which are built into the CPU, but are completely different and normally don't handle IRQs).
4) In the part about the Interrupt Mask Register (and possibly other places), you say "The 8259A Masks out all other interrupts until it recieves an End of Interrupt (EOI) signal". This isn't right - only lower priority IRQs are prevented. For example, if the PIC is waiting for an EOI for IRQ5, then IRQ4 won't be blocked but IRQ6 will be. The priorities go in this order: 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 3, 4, 5, 6, 7 (for e.g. IRQ 9 is higher priority than IRQ 3, which doesn't make sense until you think about how the cascade works). There's unused/unusual modes that mess with this (e.g. rotating priority, auto-EOI, etc), but they really aren't worth worrying about. Some OS's bypass the PIC's priorities (mask the IRQ in the PIC and send the EOI, then handle the IRQ, then unmask the IRQ) - I'm not convinced it's a good idea though (3 times as many expensive I/O port accesses).
5) I don't think you mention anywhere that for IRQs 8 to 15 you need to send an EOI to the slave PIC and the master PIC (unless it's a spurious IRQ 15, in which case you only send an EOI to the master PIC IIRC).
Hope that helps...
Cheers,
Brendan