CPU

The CPU has the following properties:

• 32-bit address bus
• 64-bit data bus
• risc design
• load/store architecture
• IEEE 754 floating point arithmetic
• little-endian
• memory-mapped I/O

General Purpose Registers

The CPU contains 16 64-bit general purpose registers (R0 to RF) used as integer, floating pointer or address registers.

Special Purpose Registers

The CPU contains the following special purpose registers:

The Status Register

The following table describes the status register:

Paging

Paging is enabled if the paging bit of the status register is set. The CPU uses a two-level page table and 4K pages. Each level contains 1024 32-bit entries. Each entry has the following format:

Protection

Protection is enabled if the protection bit of the status register is set. If protection is enabled, then the CPU uses the Segment Table register and the Access Table register to define memory segments (through the segment table) and their access rights between them (through the access table).

The Segment Table (ST) register contains the physical address of the segment table. It contains a variable number (0 to 2^29-1 entries) of 64-bit entries . Each entry has the following format:

The last entry of the table must have all bits set.

The purpose of the Segment Table is to segment the 32-bit flat address space into memory regions as well as define which region of memory can use the privileged instructions.

The Access Table (AT) register contains the physical address of the access table. It contains a variable number (0 to 2^29-1) of 64-bit entries. Each entry has the following format:

The last entry of the table must have all bits set.

The purpose of the Access Table register is to define the access rights between two segments.

The CPU contains a special cache used for quickly locating the relevant information. This cache is named the Protection Lookaside Buffer.

The following invariant is maintained by the CPU at all times:

1. if the operation is a privileged instruction, then the segment must be privileged.
2. if the operation is a read/write/execute, then source segment (the segment IP points to) must have the corresponding access right over the destination segment; valid also for software interrupts (hardware interrupts are not checked).
3. if the operation is execute:
   1. the first instruction after the jump must be a jump target.
   2. if the jump is from one segment to another segment, the jump target must be public, otherwise it can be public or private.

Any violation of the above will result in a security exception.

The protection model allows for a very fine-grained security model while maintaining the 32-bit flat address space. Typically, operating systems should setup a few entries for both tables in order to host the kernel, drivers, libraries, application code/data (read/write, read/only) and the data/return-address stacks; these entries might be held entirely in the PLB, thus not hampering performance.

The Stack

The CPU contains two stacks for security reasons:

1. the return address stack is used to store return information after a call or interrupt instruction.
2. the data stack is used to store procedure data.

Both stacks grow downwards.

Atomic Execution

An atomic load instruction causes the source memory location to be reserved.

An atomic store instruction completes successfully only if the memory reservation (previously reserved with an atomic load) is valid at the time of the store.

There is only one address reservation at each given point in time; a new atomic reservation overwrites any previous ones.

A memory reservation is cancelled if another thread/process/cpu completes a successful atomic store before the current store at the same or overlapping memory address.

The following code shows an example of an atomic increment operation:

atomic_increment:

	jt private                     ;make sure the jump is valid

	ldxd r0, ffff0000h             ;atomic load; reserve address

	ldp r1, 1                      ;load increment

        add  r0, r1                    ;increment

        stxd r0, ffff0000h             ;atomic store

        jmpc equal, atomic_increment   ;repeat if atomic store failed

Exceptions

The following table describes the CPUs exceptions:

Instruction Set

Integer arithmetic instructions use two's complement for calculations. Arithmetic operations are unsigned/signed integer, unless explicitly noted.

The following table shows the available instructions:

(C) 2007 Achilleas Margaritis