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Hi

The Intel manual says that the TLB has to be flushed (or flush a particular entry on 486+) when a page table is changed. Does this also go for mapping a new page table in, so the PDE going from 0 to some value?

Thanks
srg

Hi,

srg wrote: The Intel manual says that the TLB has to be flushed (or flush a particular entry on 486+) when a page table is changed. Does this also go for mapping a new page table in, so the PDE going from 0 to some value?

From IA-32 Intel? Architecture Software Developer?s Manual Volume 3: System Programming Guide, Section 3.11. TRANSLATION LOOKASIDE BUFFERS (TLBS):

"Whenever a page-directory or pagetable entry is changed (including when the present flag is set to zero), the operating-system must immediately invalidate the corresponding entry in the TLB so that it can be updated the next time the entry is referenced."

To me this means anytime anything is changed in any of the paging structures (page directory pointer table, page directory and/or page table). In practice (in my experience) Intel chips will work if the OS doesn't invalidate the TLB after an entry goes from 0 to something, however Cyrix chips DO NOT. For example, if an application tries to use a "not-present" page and generates a page fault, and your page fault handler allocates a page, maps it and returns to the application, then on a Cyrix CPU you will get another page fault because it thinks the page is still marked "not-present" (because the TLB wasn't flushed).

Also if you use a page directory entry to map the page directory itself (to achieve a 4 Mb map of page table entries), then there's extra considerations. In this case when a page directory entry is changed you should invalidate all pages that use this page directory entry AND the corresponding page in the page table mapping.


Cheers,

Brendan

so far, my policy is
- invlpg everytime an entry is changed in the page tables (regardless of the from/to states), or when a new page table is added
- reload CR3 everytime a page directory is altered or removed

Brendan wrote: In practice (in my experience) Intel chips will work if the OS doesn't invalidate the TLB after an entry goes from 0 to something, however Cyrix chips DO NOT.

What about bochs?

srg

Pype.Clicker wrote: so far, my policy is
- invlpg everytime an entry is changed in the page tables (regardless of the from/to states), or when a new page table is added
- reload CR3 everytime a page directory is altered or removed

I'm not going to use invlpg ATM for simplicity and 386 compatibility, but I'll add it at a later date.

srg

it looks like latest versions do have a TLB mechanism ( --enable-guest2host-tlb support guest to host addr TLB for speed) and it looks like it's there from .. 2.0 (december 2000), still i don't know if it's enabled in the mainstream binary distribution ...