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i've made some changes to my memory manager (page tables ...etc) and now i'm not able to switch to ring 3.

i'm currently using a flat segmentation mode.

i want to know the correct way to initialise a ring 3 task tss

- make the 'user' code appear in pages that are marked with 'P-U' bit and on pages which have the 'U' bit in the directory aswell.
- make the 'user' data & stack appear in pages that are tagged "PWU" in both page table and page directories
- create a DPL3 code and data segment
- create a TSS and load it with LTR, fill SS0 and ESP0 of the TSS with values that will allow the handling of exceptions/interrupts
- push a frame on the stack that mimmics the one created by a DPL3/DPL0 switch
- IRET

I am also trying ring3 switch but it keeps comming up with invalid tss (ltr appears to be working)

I have followed your advice to aladin,

but am not sure about the stack frame i should be using

I have setup the tss with only ss0 & esp0 set is this correct

heres my stack frame (in order of push)

User esp (0xc01f00)
User ss (0x20)
User Eflags (with iopl set to 3)
User cs (0x18)
User eip (0xc00000)

I then set the NT bit of flags and IRET

Hi,

pkd wrote: I am also trying ring3 switch but it keeps comming up with invalid tss (ltr appears to be working)

I have followed your advice to aladin,

but am not sure about the stack frame i should be using

I have setup the tss with only ss0 & esp0 set is this correct

heres my stack frame (in order of push)

User esp (0xc01f00)
User ss (0x20)
User Eflags (with iopl set to 3)
User cs (0x18)
User eip (0xc00000)

I then set the NT bit of flags and IRET

Are you switching to CPL=3, or doing a task switch using hardware task switching (or trying to combine both)?

If you're switching to CPL=3, then you shouldn't be setting the NT bit in eflags, and LTR and the TSS shouldn't matter. Your stack frame looks fine although I've got no way of confirming actual values, but CS and SS would need to be 0x1B and 0x23 (for CPL/RPL).

Cheers,

Brendan

i second that setting NT is not required (and will lead to invalid results: it is used only to return to a different hardware task, which selector is in the current TSS.BACK field). However,

and LTR and the TSS shouldn't matter.

triggers a warning in /dev/brain! DPL3 code will use TSS.SS0 and TSS.ESP0 to handle irqs, exceptions and INT xx, so TR must be loaded with a proper value.

Hi,

Pype.Clicker wrote:

and LTR and the TSS shouldn't matter.

triggers a warning in /dev/brain! DPL3 code will use TSS.SS0 and TSS.ESP0 to handle irqs, exceptions and INT xx, so TR must be loaded with a proper value.

You're right - I should clarify this...

The task register and TSS don't matter when switching from CPL=0 to CPL=3 (PKD's problem) as all data needed by the CPU is taken from the current/CPL=0 stack. The task register and TSS must be set correctly when switching from CPL=3 back to CPL=0 for any reason (which wasn't part of PKD's problem) .

Cheers,

Brendan

Thanks for your answers.

but I am still having problems withit (A weeks worth already)

I think it is to do with the stack (but after yet another rewrite still no good) I seem to be making the same error everytime

below is some code that id like you to double check if possible

also I have Reset up the TSS & LTR (Just in case)

Sorry about the length of my post

pkd.

;-------------------------------------------------------------------
Descriptors --

(starting at desc 0x18)

acode_desc:         ;App Descriptors
   dw   0xffff
   dw   0
   db   0
   db   0xfa
   db   0xcf
   db   0
      
adata_desc:
   dw   0xffff
   dw   0
   db   0
   db   0xf2
   db   0xcf
   db   0

sys_tss:
   dw   0x200
   dw   0x1000
   db   0
   db   0x89
   db   0x00
   db   0

;-----------------------------------------------------------------------
Page Tables --

PageDir      dd   0x201007
      dd   0x202007
               
PageTab0   dd   0xb8007      ;for basic vid Output
      dd   0x1003      ;TSS
      dd   0x2007      ;for stack
      dd   0x3003      ;for idt
      dd   0x400001   ;ker code
      dd   0x400003   ;ker as data
      dd   0x800007   ;User code

      ;entries @ 0x201800 0x200007
      ; 0x201804 0x201007
      ;set in code after copy
      ; for page dir/table memory
      
PageTab1:   dd   0x400001

;----------------------------------------------------------------------
Stack Setup --

mov   eax,0x23   ;push   ss
   push   eax
   
   push   dword   0x2800   ;push   esp
      
   pushf         ;setup flags reg
   pop   eax
      
   bts   eax,12
   bts   eax,13
         
   push   eax      ;push   flags
   
   mov   eax,0x1b   ;push   cs
   push   eax
   mov   eax,0x6000   ;push   eip
   push   eax
   
   iret

;D

Finally got it working.

Thanks to Bochs.

I was using the HLT instruction in my ring3 code with interupts disabled, and my exception Handlers Need some more work.

I also had esp & ss reversed for some reason.

Thanks to everyone for the help

pkd

pkd wrote: I was using the HLT instruction in my ring3 code with interupts disabled, and my exception Handlers Need some more work.

HLT in pl3 ? ::)
I thought this wasn't possible.......