Configuring MTRRs?
Posted: Sat Apr 24, 2004 12:51 am
Hi,
I'm currently trying to write code to configure the MTRRs.
I thought I knew what I was doing until I wrote a utility to
display the contents of these MSRs from DOS. I am
assuming DOS ignores the MTRRs and leaves them as
BIOS default settings.
On all computers I tested the video display memory
from 0xA0000 to 0xBFFFF (not LFB) is configured
as uncachable. I was wondering why the BIOSs aren't
setting this area to write combining. Is it because
SMM uses the RAM underneath? If this is the case I'd
need to disable SMM somehow (is this possible?) or
leave this area set to uncachable.
Most of the computers set ROMs as "write protected",
except for my Pentium 4 which sets the BIOS ROM as
write through. I can't figure out why write through
would be used (as opposed to write protected).
Would it be ok to use write protected on everything
from 0xC0000 to 0x100000? I won't be using any RAM
in-between the ROMs in this address range..
Thanks,
Brendan
I'm currently trying to write code to configure the MTRRs.
I thought I knew what I was doing until I wrote a utility to
display the contents of these MSRs from DOS. I am
assuming DOS ignores the MTRRs and leaves them as
BIOS default settings.
On all computers I tested the video display memory
from 0xA0000 to 0xBFFFF (not LFB) is configured
as uncachable. I was wondering why the BIOSs aren't
setting this area to write combining. Is it because
SMM uses the RAM underneath? If this is the case I'd
need to disable SMM somehow (is this possible?) or
leave this area set to uncachable.
Most of the computers set ROMs as "write protected",
except for my Pentium 4 which sets the BIOS ROM as
write through. I can't figure out why write through
would be used (as opposed to write protected).
Would it be ok to use write protected on everything
from 0xC0000 to 0x100000? I won't be using any RAM
in-between the ROMs in this address range..
Thanks,
Brendan