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I didn't understand the fields SS0 , SS1 , SS2 ESP0 , ESP1, ESP2 in the TSS .

Are they kernel stacks ? if they , what kernel stacks mean ? do they mean that the kernel running under intel platform is forced to have 3 stacks
one for each privilege level ( 0 , 1 , 2 ) ?

do the fields ESP , SS mean user stack ?

The 6th chapter of IA-32 Intel? Architecture
Software Developer?s Manual Volume 3: System Programming Guide is talking about these subjects , but as I found it is not easy book .
Is there a place where I can find this book summarized as lectures notes ?

thanks

SS0 and ESP0 are stacks for ring 0, the kernel
SS1 and ESP1 are stacks for ring 1, you could use them for drivers or something else, but no applications (of course, you make the rules )
SS2 and ESP 2 are stacks for ring 2, you could use them for the drivers or shell.
ESP and SS could mean anything, but in a TSS it means the user stack

well , thank you , however i know most of what you are saying
but i don't know what is user stack and kernel stack .

execuse me , i may express bad .

kernel stack=SS0 and ESP0 (or SS and ESP, but then in ring 0 )
user stack=SS and ESP in ring 3.
for tss's= ss0 and esp0, kernel stack
ss and esp, user stack

Okay, let's make things clear once for all:
- the CPU always uses SS:ESP to access the stack.
- when a DPLi code traps to a DPLj code (j<i), using for instance an interrupt gate, a trap gate or whatever gate you want, a stack switch automatically occurs, which causes SS:ESP to be reloaded with SSj and ESPj from the current TSS.

Thus for instance when a DPL3 program makes a system call (DPL0), the CPU will load SS with TSS.SS0 and ESP with TSS.ESP0 ... When the system call completes (e.g. on IRETD), the previous values of SS and ESP from DPL3-world are restored and TSS.SS0 and TSS.ESP0 are *not* updated by the CPU.

HTH