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PORT 0CF8-0CFF - PCI Configuration Mechanism 1 - Configuration Registers
SeeAlso: PORT 0CF8h"Mechanism 2"

0CF8d -W configuration address port (see #P0944)
0CFCd RW configuration data port (when PORT 0CF8h bit 31 is set)

Bitfields for PCI configuration address port:
Bit(s) Description (Table P0944)
1-0 reserved (00)
7-2 configuration register number (see #00878)
10-8 function
15-11 device number
23-16 bus number
30-24 reserved (0)
31 enable configuration space mapping
Note: configuration registers are considered DWORDs, so the number in bits
7-2 is the configuration space address shifted right two bits
SeeAlso: #P0945

PORT 0CF8-0CFA - PCI Configuration Mechanism 2 - Configuration Registers
Notes: this configuration mechanism is deprecated as of PCI version 2.1;
only mechanism 1 should be used for new systems
to access the configuration space, write the target bus number to
the Forward Register, then write to the Configuration Space
Enable register, and finally read or write the appropriate I/O
port(s) in the range C000h to CFFFh (where Cxrrh accesses location
'rr' in physical device 'x's configuration data)
the Intel "Saturn" and "Neptune" chipsets use configuration mechanism 2
SeeAlso: PORT 0CF8h"Mechanism 1",PORT C000h"PCI Configuration",PORT 0CFBh

0CF8 RW Configuration Space Enable (CSE) (see #P0945)
0CFA RW Forward Register (selects target bus number)

Bitfields for PCI Configuration Space Enable:
Bit(s) Description (Table P0945)
0 Special Cycle Enable (SCE)
3-1 target function number (PCI logical device within physical device)
7-4 key (non-zero to allow configuration)
SeeAlso: #P0944

Cemre wrote: well thanks anyway, probably the non-deprecated method is best for me...

Pype.Clicker wrote: btw, where did you found this ? that's the kind of thing i found only in 'pentium emulator for VME bus' document ...