Random Interrupt 0s (div by zero)

[stonedzealot]

I was running some routine tests on my keyboard code (essentially taking the floppy from computer to computer in my house seeing if it worked) and something very strange happened.

The code worked beautifully on every computer but one. The code worked on an old Aptiva, in bochs, on a new Vaio P4 as well. The computer I code on, however, spits out an Interrupt 0 (div by zero) every time I boot to it and enable interrupts.

Here's something strange too...I know the problem is in the keyboard code because everything previous to writing that works and is unchanged (IDT/PIC/IRQs, everything). So in effect, what in the keyboard code of an OS could cause a div by zero on one computer and run flawlessly on others?

The keyboard code is attached, but I have a feeling it goes a little deeper than that.

[attachment deleted by admin]

[HOS]

Code: Select all

   k_printf("Keycode: %c", 0, 10, ascii); //give us a little output   

after a quick glance i don't really understand this line. are the 0 and the 10 coordinates for the cursor position? if so, does your k_printf ever divide by one of the coordinates (namely the 0) that could cause your problem?

also, as a side note, your method for "adding" values to keep track of keyboard flag states is interesting... one question though, do you *always* want shift to cancel out caps lock? i.e. Shift+F1 with caps lock on always acts like a plain F1 press without caps lock on?

[stonedzealot]

HOS: No, the printf never divides by the coordinates. As for SHIFT + F1 = SHIFT + F1 + CAPS, you could still differentiate between them by checking caps_state and shift_state, the only place they cancel is when deciding which keymap to use.

[Pype.Clicker]

i would bet on a PIC reprogramming error. Chipsets manufacturer do not always simulate the good ole 8259 chip the same way ... for most of them, for instance, it's not mandatory to say "8086 environment" because its default or it will always route slave PIC to master PIC IRQ#2 because it's hardwired to do so, while other chipsets (AMD K6-II ones iirc) may have a more complete emulation and thus will be more sensitive to non-perfect programming ...

[HOS]

Come to think of it i had random divide by 0 interrupts myself a few months ago. what happened was that my IDT was filled with pointers to isr0, isr1... etc. and such a label looked like this:

Code: Select all

isr0:
mov eax, 0
jmp isr_main
isr1:
mov eax, 1
jmp isr_main
 ...

isr_main:
pusha
push eax
call _isr
add esp, 4
popa
iret

and so i thought my pusha was saving all of the registers but of course i had previously overwritten eax so i had to add a push eax to each isr label and a pop eax after my popa to restore eax also. before i made the correction, i had very unpredictable behavior that involved many interrupt 0's being fired... maybe in one of your assembly routines or interrupt routines you are not saving all registers properly? just a suggestion... because that code was not where i looked at first to solve the problem, i thought i had my interrupt code working fine but it turns out i had that bug for quite a while