While reading the IA-32 Instruction Set book, I find "Operation" section for each instruction most useful.
Is a complicated instruction executed in exactly the same order as depicted?
Example (excerpt from "CALL")
quote:
NONCONFORMING-CODE-SEGMENT:
IF (RPL > CPL) OR (DPL <> CPL) THEN #GP(new code segment selector); FI;
IF segment not present THEN #NP(new code segment selector); FI;
Can I assume a #GP due to priviledge level check always raises (if it does) prior to #NP during this process?
Operation order for a complex instruction
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Re:Operation order for a complex instruction
at first sight, this sounds weird, but given the fact that the 'DPL' field should still be valid when a segment is not present, i would say that yes: access to a priviledge-restricted non-present segment will raise a GPF rather than NP exception.
Re:Operation order for a complex instruction
Thanks! But that was just an example.
Wonder if the execution order in "OPERATION" section really really apply to all Intel processors the manual was written for? And not implementation dependent?
In many cases, either order of two steps can be logically viable. In the quote below, why should "null check" take place before "index check". The offset of null descriptor is 0 it can't exceed GDT limit.
CALL-GATE:
...
...
IF call gate code-segment selector is null THEN #GP(0); FI;
IF call gate code-segment selector index is outside descriptor tabel limits
THEN #GP(code segment selector); FI;
...
...
Wonder if the execution order in "OPERATION" section really really apply to all Intel processors the manual was written for? And not implementation dependent?
In many cases, either order of two steps can be logically viable. In the quote below, why should "null check" take place before "index check". The offset of null descriptor is 0 it can't exceed GDT limit.
CALL-GATE:
...
...
IF call gate code-segment selector is null THEN #GP(0); FI;
IF call gate code-segment selector index is outside descriptor tabel limits
THEN #GP(code segment selector); FI;
...
...
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Re:Operation order for a complex instruction
Imho, you could take the manual for word (provided that there are no errata) when trying to find out what occurs, but remember the CPU is *hardware*, so it does not necessarily do one check then another. It can sometimes perform all checks in parrallel and have some internal signals generated if Check1 OR Check2 is true, etc.
It makes no sense to wonder whether the 'null check' is run before or after the 'index test', as they both lead to the same result if they're true: a GPF. When consequences differ, you should be able to infer the cause from the small code given by Intel (i.e. know which tests have passed before one test failed)...
It makes no sense to wonder whether the 'null check' is run before or after the 'index test', as they both lead to the same result if they're true: a GPF. When consequences differ, you should be able to infer the cause from the small code given by Intel (i.e. know which tests have passed before one test failed)...
Now, be careful: if the offset of the NULL descriptor is 0, a limit <8 may make parts of the descriptor unavailable (okay, this shouldn't occur, but ...)Bird wrote: why should "null check" take place before "index check". The offset of null descriptor is 0 it can't exceed GDT limit.
Re:Operation order for a complex instruction
Seems quite reasonable to me...I learned much ;-)thankee
About the null descriptor...yet another mistake I made.
About the null descriptor...yet another mistake I made.