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function push(value)
{
   SP = SP - sizeof(value);
   *SP = value;
}

If not, how would I go about making a 65536-byte stack? Using 0x0 for the stack pointer seems awkward

Candy wrote: New idea about protected mode:

I'm thinking about using a single TSS for scratch space for the cpu. CR3 loading and stuff all software-methodics, but I don't know if I got this part correctly:

Using one TSS for scratch space (OS-wide...)

When a task is running, and an interrupt occurs sending it to the scheduler in cpl0, the processor stores all registers (eax - edi) on the stack for cpl3, switches to the cpl0 stack (from the TSS) and stores the return info (cs, eip, ss, esp) for cpl3 there.

Then it enters the scheduler, which swaps the stack for the kernel stack.

The kernel goes to the task choose module, switches the CR3 to that of the new tasks (thus letting the current task info change to the new tasks' info, but not changing the OS code (globally mapped)). The kernel then switches to the stack of a different process.

Upon doing an iret with cpl change, the cpl0 stack is stored in the TSS, the cpl3 info is loaded from the cpl0 stack, and the registers are loaded from the cpl3 stack, after which execution continues.

Candy wrote: Q: Wouldn't you get a stack overflow (kinda forgot how that worked...) by setting SP to 0?

Stack overflowing in PM works by checking for a page fault in the stack region right? any specific info I missed?

Candy wrote: If I pushed a 32-bit value, the stack pointer would go to 0x7FFC. Would the byte at 0x8000 exact be overwritten or not?

hmm. i'm unsure on how you plan to save eax-edi on the user stack, but this is in no way something you can do easily with an interrupt handler -- except if you check by software the SS:ESP value that has been saved by the CPU on your DPL0 stack and manually store the register values there ... however, unless you also deroute the instruction stream to a user-level "popa" instruction ...

uuh ? well, you were already on a CPL0 stack, so what's the plan for an additionnal "kernel stack" here ? can't the CPL0 stack of each process be the "kernel stack" ?

or maybe you expect the kernel stack to be available in every process while CPL0 process-specific stacks are not available globally ... hmm ... but why not just assuming that you will not access the stack between the stack-switch code (between P1.dpl0_stack and P2.dpl0_stack) and CR3 reprogramming ?

watch out: there's nothing like an automatic restore of TSS.ESP0 or TSS.SS0 by the computer: these fields are *static*, which means the CPU reads them at interrupt handling, but it never writes to them automatically.

oh sweet jesus, this stack switching dark magic is something you have to do in the ISR prologue/epilogue. There are some tutorials at www.osdever.net which should explain this with code examples.

void sched__switch_wrap() {
   // switch to scheduler stack
   asm ("movl %%esp, %0; movl %1, %%esp": "=c"(ct->esp) : "a"(kernel_t.esp));
   ct->status = SCHED_SUSP;
...
   // switch stack back
   asm ("movl %%esp, %0; movl %1, %%esp": "=c"(kernel_t.esp) : "a"(ct->esp));

   sti();

   if (ct->status == SCHED_SUSP) {
      ct->status = SCHED_RUNNING;
      asm ("addl $8, %esp; popl %ebp; iretl");

And you *have* to update esp0/ss0 in the global tss for each task for that the processor knows which esp0 to take in case of an interrupt.

also this *switching-to-kernel-stack* has to happen in the isr-prologue, right after saving all registers to the stack0 of the interrupted process/saving the esp0 value in some field for this process (a process structure).

Do you have some good books about os dev at hands?

Stack overflow can be detected by a "guard page", but you can also use the segmentation protection by using an expand-down stack segment which limit will be computed so that the "valid stack addresses" start at the limit (and go up to 0xFFFFFFF) ...

The advantage of this technique over pure paging wwwprotection is that you still can handle a stack overflow for the kernel stack if you dedicate a TSS to the handling of Stack Fault exception.