error: undefined references

[beyondsociety]

I'm trying to write a c function that adds my interrupt handlers in c and when I compile it with gcc, it gives me a undefined reference error. I have included the necessary files that are needed to run the function, but I still get that error. What could be the problem?

[Tim]

Have you added all relevant object (.o) file names to the linker command line?

[beyondsociety]

Yes. I compile like this:

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gcc -ffreestanding -fno-builtines -Wall -c *.c
ar -rsc kernel.lib *.o
ld -T linker.ld -o kernel.bin stub.o kernel.lib

Kernel.bin = first stage bootloader
stub.o = second-stage loader that is compiled to coff and linked to the c kernel.

I wonder if theres a problem with my kernel.lib file as I know code slasher had problems in the past with trying to create a libary using ar -rsc?.

[Tim]

Looks OK to me, but:
[x]-fno-builtines should be -fno-builtins
[x]I use ar rsc, not ar -rsc. I don't know whether the - is breaking anything.
[x]It looks like you're linking stub.o twice: once in kernel.lib and once on the linker command line. I would name each source and object file on the command line explicitly instead of using wildcards.

[Therx]

Can you use wildcards when passing to gcc or ar?
If you can it will make my linker script a lot tidier.

Pete

[Tim]

Yes. As Unix programs, they expect globbing (i.e. expanding) of wildcard arguments. However, I wouldn't recommend it, since if you're not careful it will drag in any .c or .o files which happen to be lying around. Also, I'm not too keen on the ar approach, as I think it will never remove old .o files from the library. For instance, if you delete or rename a source file, the old object file will remain inside the library forever.

[mystran]

You probably don't want to use wildcards in the command line. In Linker script it probably doesn't hurt, but in make file I'd list all the objects into a variable like OBJECTS, use one rule for generating .o from a .c file, and finally put the $(OBJECTS) into the final line for LD.

If you don't want to have your make-script so noisy, you can always put @ before any commands you don't want displayed. Example:

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.c.o:
        @echo "Compiling $< ..."
        @$(CC) -c $(CFLAGS) -o $@ $<

This will only then say "Compiling foo.c..." but still displayes any errors/warnings from GCC, which there should be none anyway.

[beyondsociety]

After doing some research and looking through the code, I figured out what was wrong. I forgot to add a underscore to the asm function which is needed since i'm using coff.

Is there a way to seperate the .o files into seperate folders like one folder for .o files that were created by the assembler and one folder for the .o files that were created with gcc, then store them together in the library and then link them with ld?