Early NMI handling...
Posted: Wed Jul 02, 2003 8:15 am
A quote from the Intel manuals, Vol. 3, chapter 9.7.2 "NMI Interrupt Handling":
...I still don't have a clue what actually happens if a NMI hits during early startup. I don't like to take chances ("won't happen too often...") so I am asking for experience, additional info links, whatever...
???
OK, so this is BIOS / chipset / motherboard voodoo. I understand why Intel doesn't actually tell the BIOS manufacturers how to do their work, in their CPU manuals, but...The NMI interrupt is always enabled (except when multiple NMIs are nested). If the IDT and the NMI interrupt handler need to be loaded into RAM, there will be a period of time following hardware reset wen an NMI interrupt cannot be handled. During this time, hardware must provide a mechanism to prevent an NMI interrupt from halting code execution until the IDT and the necessary NMI handler software is loaded. Here are two examples of how NMIs can be handled during the initial states of processor initialization:
* A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an NMI interrupt to be handled immediately after reset initialization.
* The system hardware can provide a mechanism to enable and disable NMIs by passing the NMI# signal through an AND gate controlled by a flag in an I/O port. Hardware can clear the flag when the processor is reset, and software can set the flag when it is ready to handle NMI interrupts.
...I still don't have a clue what actually happens if a NMI hits during early startup. I don't like to take chances ("won't happen too often...") so I am asking for experience, additional info links, whatever...
???