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ASM cmp operation.:
Iv known ASM for sometime. Iv used
cmp AX , BX
jz
before, but I need to use
cmp AX , BX
ja
Now which order they come in doesnt matter for jz but when I write
cmp AX , BX
ja
I came the horrid concustion that I dont know if thats jump if AX is above BX or jump if BX is above AX. Which one is it?

GDT? Global Discripter Tabe?:
Global Discripter Tabe? What IS it? I know its used to store information about memory locations, like where a segment starts and what permissions a prossess has but what IS it? Ive been through the source code for 7 operating systems and the GDT is differnt in each one. In some of the more advanced operating systems its implemented as a array of segment discripters.

The GDT is loaded using the ASM instruction LGDT [GDT].

If its loaded by the CPU like this doesnt it have to be in a standared format? Is it in a special format so the CPU can use it or is it just a place to hold discripters, that the OS gives to the CPU in some other way? In that case how is it done?
And what is TSS?

Thank you for your time,
Arrummzen

You will find all the answers you need by going to http://developer.intel.com/ and downloading the Pentium manuals.

Arrummzen wrote: I came the horrid concustion that I dont know if thats jump if AX is above BX or jump if BX is above AX. Which one is it?

Volume 2 of the Intel manuals (Instruction Set Reference).

GDT? Global Discripter Table?

Volume 3 of the Intel manuals (System Programmer Manual).

but what IS it?

An 8-byte collection of pointers and flags.

In some of the more advanced operating systems its implemented as a array of segment discripters.

Which is correct.

If its loaded by the CPU like this doesnt it have to be in a standared format? Is it in a special format so the CPU can use it or is it just a place to hold discripters, that the OS gives to the CPU in some other way?

It is in a standard format. (Vol. 3...)

And what is TSS?

Task segment selector (?). The IA32 supports multitasking (i.e., saving of context) in hardware. The TSS is the data structure holding one task state.

Sorry but either of those is too complex to be described in short here. If you do OS coding for the IA32, you *need* the Intel manuals.