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Hi all!

Ok, I've the IDT loaded and to prove to myself it worked I invoke int 0xD...however it does not do anything...
here's the code...

patch_idts:
mov esi, ISRTable
mov cx, 34
mov edi, idt
fill_idts:
mov ax, [esi]
mov [edi], ax
shr ax, 16
mov [edi+6], ax
add esi, 2
add edi, 8
loop fill_idts
xor ebx, ebx
mov bx, cs
shl ebx, 4
mov eax, idt
add eax, ebx
mov [idtr+2], eax
lidt [idtr]
retn;

cpu_exception13:
cli
SAVE_REGS ; macro to pushad, push ds, es, fs, gs
push cs
mov eax, CODE_SELECTOR
push eax
pop cs
mov eax, DATA_SELECTOR
mov ds, eax
mov fs, eax
mov gs, eax
mov ss, eax
xor eax, eax
mov ah, 0x1b
mov al, 'D'
mov ebx, 1 ; Column
mov edx, 15 ; Row
push ebx
push edx
push eax
call WriteChar32
pop cs
sti
RESTORE_REGS ; Macro to pop gs, fs, es, ds, popad

WriteChar32:
pop esi ; Pop Callee's return address
mov eax, 0xb8000
mov es, eax
pop ebx ; Attribute/Char
mov [Attr], bx ; save it for now
pop ecx ; Row
dec cx
mov [YPos], cx
pop eax ; Column
push esi ; Push Callee's return address
dec ax
mov [XPos], ax
xor edx, edx
mov dl, cl
mov bx, dx
shl dx, 6
shl bx, 4
add dx, bx
xor edi, edi
add edi, edx
mov bx, [XPos]
add edi, bx
shl edi, 1
mov eax, [Attr]
stosd
retn

in data section I have
ISRTable
dw cpu_exception0 ; INT 0x0
dw .....
dw cpu_exception15 ; INT 0xF
dw reserved ; From INT's 0x10->0x1F
dw ....
dw isr_irq0 ; INT 0x20
dw isr_irq1 ; INT 0x21

Question is, is my isr correct? What I'm expecting is a 'D' to appear at line 15, column 1...this is decremented by 1 to cater for offset 0 in video memory. Any pointers to where I'm going wrong. Funny thing is a) it aint triple faulting or anything b) I have WriteChar code as 16 bit (identical with 16bit registers and it works fine!)

Thanks,
Tommie.

where is your IDT/ISR locted in memory because you might need to split the address of the ISR into two parts...

Hi Slack,
the cpu_exceptionN (where N is from 0-15) are located after the Jmp to protected mode...see my attachment I posted in the previous posting, even though it's modified, I am under the impression that the code is being executed alright like when I invoke int N, it pokes the video memory and the exceptions are caught, which is fine....however I wish to have the isr execute code inside it...but it triple faults when that happens....what do you mean by splitting the address of ISR into two parts? something like this?
cpu_exception13:
; save regs et al
jmp CODE_SELECTOR:int_routine13
; restore regs et al
iretd

I will however endevour to post the updated code as attachment.....

Thanks,
Tommie.

your code looks kinda confusing and complicated to me. try something like this:

---------------------------DATA---------------------------
;---IDT register information---
IDTpntr:
IDTlim dw IDTend - IDT - 1 ;limit
IDTbase dd IDT ;base

;---int 0---
int0LOW dw 0x00 ;low offset
dw 0x0008 ;code selector
db 0x00 ;always zero
db 0x8E ;descriptor settings
int0HIGH dw 0x00 ;high offset

Hi Slacker,
apologise for delay....here's the code ...
; initialisation of 8259, A20 etc.interrupts are disabled!
   jmp CODE_SELECTOR:ProtMode
[BITS 32]
ProtMode:
   mov eax, DATA_SELECTOR
   mov ds, eax
   mov fs, eax
   mov gs, eax
   mov ss, eax
   ; Set up stack pointer
   xor eax, eax
   mov ax, sp
   mov esp, eax
   ;
   ;....
   sti ; enable interrupts!
   int 0xD ; This invokes cpu_exception13!
; cpu_exception1-12 are the same, BUT
; it displays respective exception code 1...F in their
; consecutive columns, ie. if inx 0x1...int 0xF invoked...
; there should be 123456789ABCDEF on first line of display etc...
cpu_exception0:
   ISR_SAVE_REGS
   cli
   mov eax, LINEAR_SELECTOR
   mov es, eax
   mov byte [es:dword B8000], '0'
   mov byte [es:dword B8001], 0x1B
   sti
   ISR_RESTORE_REGS
; made changes to cpu_exception13
cpu_exception13:
   push ax
   mov ax, 0xD
   push bp
   mov bp, sp
   push ds
   push es
   pushad
   push word [ss:bp+4] ; Error Code
   push dword [ss:bp+8] ; IP
   push word [ss:bp+12] ; CS
   push ax ; Exception #
   xor ax, ax
   mov ah, 0x1B
   mov al, 'D'
   mov bx, 1 ; Column 1
   mov dx, 15 ; Row 15
   push bx
   push dx
   push ax
   call WriteChar32
   add sp, 10 ; To account for Error Code, IP, CS
   popad
   pop es
   pop ds
   pop bp
   pop ax
   iretd
what happens on screen when I comment out the rest of int 0x0...int 0x21 except for int 0xD, is I get 8 as result of explicitly invoking 'int 0xD', '8' appears on screen, somehow it caused a double fault and then resets itself a la triple fault, this proves to me the exceptions are caught! However, I commented out the code i.e. cpu_exception13, and made it look like the others, and when I invoke other int's 0x0...0x21, I get the following 0123456789ABCDEFTK
T for Timer (int 0x20), K for kbd (int 0x21) which appears fine and dandy....
Why? Is my WriteChar32 routine as posted previously dodgy or is it my stack that got trashed and as a result the code somehow jumped off into the woods never to be seen again? Any hints, clues etc?

Thanks Slacker for ur reply!
Tommie.

GPF, namely exception 13, pushes an errorcode onto the stack. GPF is also a fault, namely it pushes the CS/EIP pair of the faulting instruction onto the stack so an iretd returns to execute the instruction again, not the following instruction.

Now all that holds true if, and only if, the processor is calling the interrupt because a GPF has actually happened. When you call interrupt 13 in your code you're using a software interrupt. A software interrupt will give no error code, and push the CS/EIP pair of the following instruction. IE it's not going to behave the same way as the exception would.

So yes, it's likely you've screwed up your stack. Your OS should pretty much never permit the reserved interrupts to get called as software interrupts.

If you need to test the GPF exception then the easiest way is probably to just to attempt a far jump into the null selector. Things will fall over rapidly at that point, but you'll raise a GPF exception for sure .

Thanks Curufir for that, I did suspect that the stack got trashed somewhere....I have searched hi and lo in looking for a good example of idt creation and trapping written in NASM, the examples/tutorials I've seen are where the handlers are written in C! :-\ What would be the best way for the handlers to ensure the stack doesn't get trashed? and how would I go about calling a generic routine to print a string such as "Exception occurred ...." or similar inside the handler in NASM?

I will be posting the complete code for scrutiny tomorrow, if anyone would care to see how I've fared as this is my first pmode prog. in assembly, yes, my assembly is a bit rusty after programming in C for years.... I am kinda limited on resources on this PC for net access so will use the college computers....

Thanks!
Tommie. ;D

Guys,

I've attached the code...ok the filename is a bit of a misnomer cos I want to start off small first to ensure I understand what I'm doing...hey that's progress!! Would you care to take a peek at the code and tell me where I'm going wrong, I've commented out the invocation of software int's....and an 8 appears on screen for double exception!!!! Is there something gone screwy with the stack?? Any help would be much appreciated!

[attachment deleted by admin]

a mistake i made for the first time after i remapped PICs was not having an ISR for int 0x20 which was the timer that fired 18 times a sec..so i got an error from that..also if your int 0x08 works then the error is proboly not from your IDT setup...

Interesting reply Slacker , odd though, cos nothing is invoked, as for the double fault '8' appearing on screen, the isr_irq0 handler seems ok or is it? I do know that for handlers, it's job is to push all regs on stack, disable interrupts, do what ever, in this case print a T for timer, re-enable interrupts, pop all regs and iret which is what it is supposed to be doing, the odd thing that you mentioned is that the timer fires off every 18 times a second, even though 'T' does not appear. ??? ... sigh....I feel like drowning in this maze of pmode programming....I have debugged this countless of times and feel like jacking it in :'( ....enlightenment anyone before I give up? :-[

Many thanks for your reply slacker,
Tommie.

at what piece of code does the fault occur? narrow it down using bochs or 'hlt'. also some some reason when i wrote my ISR's whenver i would pop GS,ES,or FS i would get an exception 6 invalid opcode.

I was thinking of masking off all interrupts on 8259 to make sure that irq_isr0 & irq_isr1 does not fire for the moment, if I get nothing on screen then it would be safe to assume my irq_isr0/1 routines are screwing up somewhere, if not that, put a hlt in some part of the code, if all else fails, I'll comment out the idt stuff to ensure it works, and if that works, then I would place money on something went screwy with idt and idtr.... it was posted earlier about splitting addresses of the handlers, are we talking about something similar to patching up the lo and hi offset of the handlers e.g
mov dx, cs
push dx
shl dx, 4
; use dx as the high offset in the idt table
pop dx
shr dx, 16
; use dx as the low offset in the idt table

How does that sound?
Thanks slacker
Regards, Tommie.

to split the address:

addr & 0xFFFF low
addr>>16 high

Hi Slacker, and good afternoon, it's 12:49pm here in Limerick, Ireland,
Ok, I've tried the following situs...
a) disabled ints in pmode, no exceptions
b) re-enable ints in pmode, thn hlt'd, exception 8 appears
c) masked off all ints thru 8259 (0xff to master/slave), w. ints enabled, no exceptions, this was expected
after doing the scenarios, there's a ? mark over whether the code is right or not
;
patch_idts:
   mov esi, ISRTable
   mov cx, 34
   mov edi, idt
fill_idts:
   mov ax, [esi]
   mov [edi], ax
   shr ax, 16
   mov [edi+6], ax
   add esi, 2
   add edi, 8
   loop fill_idts
   ; Adjust ebx/eax for linear addresses of code
   xor ebx, ebx
   mov bx, cs
   shl ebx, 4
   ; Patch up IDTR address of IDT
   mov eax, idt
   add eax, ebx
   mov [idtr+2], eax
   mov si, idt_msg
   mov bx, 1
   mov dx, 11
   mov cx, idt_msg_len
   push si
   push bx
   push dx
   push cx
   call WriteString
   retn

section .data
idt_msg db "IDT's patched relative to Kernel Code/Data Segment and loaded."
idt_msg_len equ $-idt_msg
;
ISRTable
   dw cpu_exception0
   dw cpu_exception1
   dw cpu_exception2
   dw cpu_exception3
   dw cpu_exception4
   dw cpu_exception5
   dw cpu_exception6
   dw cpu_exception7
   dw cpu_exception8
   dw cpu_exception9
   dw cpu_exception10
   dw cpu_exception11
   dw cpu_exception12
   dw cpu_exception13
   dw cpu_exception14
   dw cpu_exception15
   dw reserved_exception ; 16
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception
   dw reserved_exception ; 1F
   dw isr_irq0 ; int 0x20
   dw isr_irq1 ; int 0x21
; Interrupt Descriptor Table
idtr: dw idt_end - idt - 1
    dd idt
idt:
%rep 64
   dw 0
   dw CODE_SELECTOR
   db 0
   db 0x8E
   dw 0
%endrep
idt_end:
;
section .bss
;

Thanks,
Tommie.

try setting up your IDT in the same manner as the code i posted earlier...its easier to debug