Multitasking Problem

[chrisa128]

Hi all,

I have run into a problem with my multitasking, I have included bochsout.txt and will be able to give source on request.

The actual kernel triples faults when I try to use the "ltr ax" command.

Thanks

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[Tim]

The problems looks pretty obvious:

Code: Select all

00004346673i[CPU  ] selector->index*8 + 7 = 65367
00004346673i[CPU  ] gdtr.limit = 39
00004346673i[CPU  ] fetch_raw_descriptor: GDT: index > limit

You're trying to use LTR with a junk value.

[Pype.Clicker]

well, it looks like the selector you try to load isn't valid. Probably some assembly mistake as eax=0x30... maybe you're doing ltr [eax] instead of ltr ax ... or something like that ...

[chrisa128]

Thanks,

My loadTR function is "mov ax,[esp+8]", "ltr ax" which I think should be ok.

I will post the code to my LoadTaskDescriptor when I get home to my development computer.

[Pype.Clicker]

do you by any chance have your interrupts enabled ?
could a handler destroy your eax value ?

[chrisa128]

Interrupts are enable after I attempt to do this!

Code is as follows in the main function...

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   pmproc = AllocThread (PID_PROCESS_MANAGER, PM_PRIORITY, 0, 0, 0, KERNEL_CODE, KERNEL_DATA);

   SetTaskDesc (gdt.seg + PID_PROCESS_MANAGER, (unsigned long)pmproc, 0x67, 0);

   LoadTR (PID_PROCESS_MANAGER>>3);

The actual function Alloc Thread is in the attached source file.

SetTaskDesc is equal to the following...

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_SetTaskDesc
   push ebp
   mov ebp, esp
   push ebx
   
   mov ebx, [ebp+8] ;struct SegmentDescriptor *s

   mov eax, [ebp+16] ; ulong limit
   and eax, 0x000f0000 
   
   mov edx, [ebp+20] ; char dpl
   shl edx, 13
   and edx, 0x00006000
   
   or eax, edx
   
   mov edx, [ebp+12] ; ulong base
   shr edx, 16
   and edx, 0x000000ff    
   
   or eax, edx
   
   mov edx, [ebp+12] ; ulong base
   and edx, 0xff000000   
   or eax, edx
   
   or eax, 0x00008900
   
   mov [ebx+4], eax
   
   mov eax, [ebp+16] ; ulong limit
   and eax, 0x0000ffff   
      
   mov edx, [ebp+12] ; ulong base
   shl edx, 16
   or eax, edx
   
   mov [ebx], eax
   
   pop ebx
   pop ebp
   ret

And LoadTR is equal to the following...

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_LoadTR
   push ebp
   mov ebp, esp
   
   mov ax, [ebp+8]
   ltr ax

   pop ebp
   ret

Thanks for your help in advanced

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[Tim]

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   SetTaskDesc (gdt.seg + PID_PROCESS_MANAGER, (unsigned long)pmproc, 0x67, 0);

   LoadTR (PID_PROCESS_MANAGER>>3);

This looks suspect. A ring 0 GDT selector has the same numeric value as its offset within the GDT. I don't think you need the >>3.

[chrisa128]

Still Triple Faults, I think I may have messed up the AND's in SetTaskDesc. My kernel is loaded at 0x00100000 by Grub, can you please look at this, I think I have got it right but I am not sure.

[Tim]

Why did you write SetTaskDesc in assembler? All that code could be a couple of lines of C.

[chrisa128]

It be great if you could translate to C for me, I started my coding in Assembler and so occasionally use Assembler where I don't feel I can write the C to do the same thing.

[Tim]

You could start by declaring variables for each of the registers you use. Then, you can replace each instruction by the equivalent operation in C. After that, simplify the routine by combining operations, and give the variables more descriptive names.

[chrisa128]

Ok, I decided I don't want to move it to C for design reasons. However I still need to sort the problem causing it to triple fault.

Please can some have a look at the SetTaskDesc AND statements.

Like I have said the kernel is loaded at 0x00100000,
my IDT table is at 0x00090000
the first user task would be loaded at 0x00200000

Thanks for any help

[chrisa128]

Anyone, please help, I want to get this done so I can carry on with my file system.

is this correct order for the TSS

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struct TSS
{
   unsigned short backlink, pad0;
   void *esp0;
   unsigned short ss0, pad1;
   void *esp1;
   unsigned short ss1, pad2;
   void *esp2;
   unsigned short ss2, pad3;
   unsigned long cr3;
   void *eip;
   unsigned long eflags;
   unsigned long eax;
   unsigned long ecx;
   unsigned long edx;
   unsigned long ebx;
   void *esp;
   void *ebp;
   void *esi;
   void *edi;
   unsigned short es, pad4;
   unsigned short cs, pad5;
   unsigned short ss, pad6;
   unsigned short ds, pad7;
   unsigned short fs, pad8;
   unsigned short gs, pad9;
   unsigned short ldt, pad10;
   unsigned short debug, iomap;
};

[distantvoices]

here is a proposal for a tss-structure. I use it and it does its job perfectly.

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ushort_t = unsigned short - 16 bits in length
uint_t = unsigned int - 32 bits in length


typedef struct {
    ushort_t   backlink, __blh;
    uint_t   esp0;
    ushort_t   ss0, __ss0h;
    uint_t   esp1;
    ushort_t   ss1, __ss1h;
    uint_t   esp2;
    ushort_t   ss2, __ss2h;
    uint_t   cr3;
    uint_t   eip;
    uint_t   eflags;
    uint_t   eax, ecx, edx, ebx;
    uint_t   esp, ebp, esi, edi;
    ushort_t   es, __esh;
    ushort_t   cs, __csh;
    ushort_t   ss, __ssh;
    ushort_t   ds, __dsh;
    ushort_t   fs, __fsh;
    ushort_t   gs, __gsh;
    ushort_t   ldt, __ldth;
    ushort_t   trace, bitmap;
}
tss_t;

there are no unsigned LONG fields.

May you comment your asm code a bit? I get a little clue what it does but it would help if there were comments at strategic places.

stay safe

[chrisa128]

00004185187i[CPU ] selector->index*8 + 7 = 391
00004185187i[CPU ] gdtr.limit = 39
00004185187i[CPU ] fetch_raw_descriptor: GDT: index > limit

Strange that, how I started looking for problems in my TSS code. If my GDTR limit is 39 how can I increase this?

Thanks