paging
Posted: Wed Apr 04, 2001 11:00 pm
Hi out there..
I want to implement paging in my OS, but i dont
know exactily how to do this. I tell you my
paging implementation idea, and could you tell
me i what point i am wrong ? thanks...
ok..
i think there must be a data structure or bitmap
in the kernel which keeps track of which pages in
physical memory are used, and which not.
when a new process is created, some of this free
phyiscal pages, are mapped to virtual adresses
into a pagetable which is unice to a process.
in the stucture which keeps track of physical
memory, these pages are marked as "used".
when a switch to a process acours, its pagetable
base is loaded into CR3. when a process terminates,
the physical pages of the process are marked as
free in the kernel data structure which keeps
track of physical memory.
for each process the physical memory is mapped to
the same virtual adress (e.g. 0x100), so that all
processes think they're running at 0x100.
is that a right and common paging implementation ?
but there is still a open question:
if a interrupt accours, then in the IDT there
would be a Task Gate, and a Task switch accours..
but how can dis work if the pagetable of the running
process is in CR3 ??
thanks for your help !
I want to implement paging in my OS, but i dont
know exactily how to do this. I tell you my
paging implementation idea, and could you tell
me i what point i am wrong ? thanks...
ok..
i think there must be a data structure or bitmap
in the kernel which keeps track of which pages in
physical memory are used, and which not.
when a new process is created, some of this free
phyiscal pages, are mapped to virtual adresses
into a pagetable which is unice to a process.
in the stucture which keeps track of physical
memory, these pages are marked as "used".
when a switch to a process acours, its pagetable
base is loaded into CR3. when a process terminates,
the physical pages of the process are marked as
free in the kernel data structure which keeps
track of physical memory.
for each process the physical memory is mapped to
the same virtual adress (e.g. 0x100), so that all
processes think they're running at 0x100.
is that a right and common paging implementation ?
but there is still a open question:
if a interrupt accours, then in the IDT there
would be a Task Gate, and a Task switch accours..
but how can dis work if the pagetable of the running
process is in CR3 ??
thanks for your help !