some questions about software task switching and TSS

[earlz]

Ok I am finally implementing multitasking and have decided to do it by software task switching
now my questions

1.Is it possible to have full task switching(ring 0 and ring 3) tasks with just 1 TSS(I only need 32bit)
2.when their is an interrupt or something does it fill all the fields of the TSS like general registers and such
3.at iret are the registers and such loaded from TSS or stack
4.should i change cross-ring stacks with each task
5.If i have my segments(including SS) ring0 then will it still use the ring0 stack in the TSS
6.is having my ring 1 and 2 stacks in the tss use a ring3 segment bad



I'll probably have more later but thats it for now

edit:

7.(kinda offtopic)if you change a gdt entry then do you have to reload the segment [so it is cached maybe or something]

[digo_rp]

give me your e-mail that I send to you my source, I got both ones software either hardware taskswitching, ring0 to ring3 isn?t much but I think should helps you alot

[earlz]

email: hack9483_NO_CANNED_MEAT -AT- NO_CANNED_MEAT.gmail.com


thanks in advance

[JAAman]

#1 yes, most people use 1 TSS per CPU (if you only support 1 CPU, you will only need one)


#2 no, (the CPU will never write to the TSS except the busy bit when using soft-switching) the only fields of the Pmode TSS that are used in soft-switching, is the SS:ESP of each ring used in your OS (except ring3 -- stored on stack) and the permission bit-map (if present)


#3 from the stack


#4 normally, each process will have 2 stacks (1 ring 3, and 1 ring 0) -- more if you use ring 1&2


#5 you must have a separate SS for each ring -- the one you use in ring3 cannot be a ring0 segment, or you will get a GPF -- the CPU will automatically load the ring0 SS from the TSS each time there is a ring change into ring0 (you need this anyway, as each SS selector must match the ring it is used in)


#6 i dont think you can do that -- though im not looking at the intel docs atm, -- you should have a separate one anyway


#7 segment selectors are loaded into the segment registers, to change the entry for a segment which is already loaded into a register, simply reload the register with the same selector -- if that selector is not currently in use, no change is required -- the CPU does not cache selectors




btw:
TSS information i presented here applies only to the PMode TSS -- the LMode TSS is completely unrelated, and is used very differently (and all of it is relevent)

[earlz]

yea thats what I'm wanting for this is pmode

#2 no, (the CPU will never write to the TSS except the busy bit when using soft-switching) the only fields of the Pmode TSS that are used in soft-switching, is the SS:ESP of each ring used in your OS (except ring3 -- stored on stack) and the permission bit-map (if present)

so the registers and other stuff stored in the TSS is just their if your going to use hardware task switching?

[earlz]

Well I got some of it working and am trying to just make a simple ring3 task(no interrupts) but I can't do an iret to switch tasks

with this code

Code: Select all

          gdt_set_gate(15,0,0xFFFFF,0xFB,0xCF); //testing code segment
     	gdt_set_gate(16,0,0xFFFFF,0xF3,0xCF); //data segment --num,base,limit,access,granularity
          __asm(".intel_syntax noprefix\n"
          //"mov ds,0x80\n"

          "push 0x80\n"
          "push esp\n"
          "pushfd\n"
          "push 0x78\n"
          "push cs:tmp\n"
          "mov ax,0x80\n"
          "mov ds,ax\n"
          "mov es,ax\n"
          "mov fs,ax\n"
          "mov gs,ax\n"
          "mov ss,ax\n"
          "iret\n"
          "tmp:\n"
          "hlt\n"
          ".att_syntax\n");

with that code I get "load_seg_reg(): dpl != CPL"
and if I don't change SS then I get "iret: Return with DPL != RPL. #GP(selector)" and I thought with iret you could switch priveledge from 0 to 3(well I know you can)

[JAAman]

so the registers and other stuff stored in the TSS is just their if your going to use hardware task switching?

that is correct

with that code I get "load_seg_reg(): dpl != CPL"
and if I don't change SS then I get "iret: Return with DPL != RPL. #GP(selector)" and I thought with iret you could switch priveledge from 0 to 3(well I know you can)

yes, iret will change privilege level -- i didnt check your discriptors but all your segment selectors (at minimum, CS, SS, and DS) must be loaded with ring3 segments


dpl != CPL -- this prob means your loading your stack with a segment whose discriptor is set to ring0 -- and your currently in ring3

dpl != rpl -- this means that your attempting to load a segment where the selector and discriptor dont match


the selector you are placing on the stack for the SS register, is 0x80 -- the last 2 bits are 00 -- this means the RPL (requested privilege level) is ring0, which will cause an error in ring3 (thus your dpl != cpl) however, if you change this to a ring3 rpl (the same selector would be 0x83) then you may get a dpl != rpl if the segment discriptor is set to ring0 -- both need to be ring3, which is why you need separate segments for each ring

check intel volume3a, section 4.5 for more detailed information