DPL 0 => DPL 3 ?

[?]

How to switch to User Mode without any TSS (software-task-switch). (I know I will need TSS later to go back to DPL0 with Interrupt or whatever).

This is my example code:

pushfd
pop eax
or eax, 16384 ; Sets NT flag to IRETD work
push eax
popfd


;mov ax, 48
;mov ss, ax
;mov esp, 0x2000

push dword 0x00 ; eflags
push dword 100011b ; CS (32 + 3)
push dword Begin ; EIP
mov ax, 40
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
iretd

Begin:
mov byte [DS:0xB8000], ' '
mov byte [DS:0xB8000], 'U'
jmp Begin


32 - in GDT standard 4GB code DPL3 segment descriptor
40 - in GDT standard 4GB data DPL3 segment descriptor
48 - in GDT 8kb expand-up segment DPL3 descriptor

And this isn't working :/.
Bochs is reseting PC, and in bochsout I can read only:
TR is invalid.

I am fighting with that 2 days.
So I think I need to set this f*** TSS ;/. But could somebody explain me what fields in it I need to save and with what data to switch to that DPL3?
And what additional thing I need to do (LTR etc.)?

PS: What a stupid thing that segments, why the could not do just paging ;/.

[Da_Maestro]

Best not to worry about user mode until you get the rest of your kernel running. In general a TSS is nessesary in almost every operation to do with protection.

The Intel Docs are a good source of info (can someone link?)

[?]

I was reading Intel Manuals but still can't run in DPL3 ;/. I want to know how to run process (begin execution in DPL3) because I want to write multitasking, and how I could write it if I can't swith even to DPL3 :[. So anybody could help to explain me the steps?

[digo_rp]

If you want to DPL3 in software taskswitching you only need one TSS just TSS.SS0 and TSS.ESP0
this is the kernel stack those fields are same used in both software/hardware taskswitching. and you should use DPL3 GDT entrie too something like

gdt selector | 3 like that:

Ring0
add_task("cmd", 0x08, (dword)&cmd, 0x10, 0x202L, 3);
Ring3
add_task("timmer a", 0x18 | 3, (dword)&task_a, 0x20 | 3, 0x3202L, 7);

GDT.C

/* 1 - 0x08 -- code descriptor */
gdtindex++;
set_gdt_entry(gdtindex, 0, 0xFFFFFFFF, ACS_CODE, 0xCF); /* 0x9A */

/* 2 - 0x10 -- data descriptor */
gdtindex++;
set_gdt_entry(gdtindex, 0, 0xFFFFFFFF, ACS_DATA, 0xCF); /* 0x92 */


/* 3 - 0x18 -- code segment for tasks */
gdtindex++;
set_gdt_entry(gdtindex, 0, 0xFFFFFFFF, ACS_CODE | ACS_DPL_3, 0xCF);

/* 4 - 0x20 -- data segment for tasks */
gdtindex++;
set_gdt_entry(gdtindex, 0, 0xFFFFFFFF, ACS_DATA | ACS_DPL_3, 0xCF);

[Da_Maestro]

Check out the linux source code as well. That has some great code to look at and learn from

[?]

Yeah great :/.
Linux is:
A - monolith
B - C coded

I am writing in ASM, and trying to write microkernel. So I am just asking for some description how IRETD works and how to use It. Thanks.

[JAAman]

lookup 'iret' in the intel vol 2a and reread the entire vol 3 chapter 6 (portions of chapter 5 may also be relevent)

the problem you are having is:
the code switches to ring3 (user code)
a soft, hard, or firm interupt occures (most likly either your clock (irq0) or an exception (firm-int))
the CPU must switch back to ring0 to handle this condition
the CPU needs a clean, ring0, stack to operate in
it looks in the TSS to find the address of the kernel stack
doesnt find a kernel stack, and therefore creates another error (a double-fault, since it is a fault while fetching an exception handler)

the double-fault handler specifies ring0 (or there isnt one)
the CPU trys again to find a valid ring0 stack (and again fails)
this causes a 3rd exception (also called a tripple-fault) which on most (but not all) computers, will cause the system to reboot -- bochs will either reboot or halt and show an error depending on you config settings


you dont need to do much of anything with segments

the TSS structure containing the kernel stack address and some permission information (until you are more advanced, you dont need to do anything with that), and is required to handle switches between ring3 and ring0 (and will tripple-fault if you switch into ring3 without one)

the only fields you will need to fill (in PMode) is ss0:esp0 (assuming you are using software-switching -- if you are using hard-switching, you will need more)

[?]

I just do it finally on my own, without any TSS.

I do this:

mov ax, 40
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax

push dword DPL3_SS | 3
push dword DPL3_ESP ; Is this ESP of process stack?
push dword DPL3_EFLAGS
push dword DPL3_CS | 3
push dword DPL3_EIP
iretd

I was fighting with that so long because someone on this forum , or on osdcom.info write that there need to be pushed DPL3_DS not DPL3_SS on startup and it was driving everything to go down ;/.

It also doesn't work when I set up Paging :[ (all memory maped thesame as it is in real).

Now I will try to write proper DPL3-> DPL0 switch, so I know I need to start thinking about TSS's :].

I have another question. Do I need to set NT flag when going to DPL3 when I am using IRETD (and I have TSS)? Because I was doing tests with seted up TSS and the switch was working correctly but when I turn On NT flag, Bochs returned:
"iret: TSS selector points to bad TSS"

SMALL EDIT:

I have done problem with paging (I was forget to set up bit U/S ).

[JAAman]

shouldnt -- i think if NT is set, then the CPU needs the busy flag in the TSS to be set (iirc, didnt look it up)