EPT page tables vs hypervisor process's page tables
Posted: Thu May 22, 2025 12:20 am
Consider a system virtualization like qemu/kvm under Linux and assume EPT nested translation is enabled on the host.
From Intel 64 SDM, it seems to me that EPT paging-structures (both 4-level and 5-level) are actually different from "standard" paging structures available in 32-bit protected mode and IA-32e mode (64 bit and compatibility submodes).
Hypervisor/VMM like qemu allocate guest physical memory to a VM from their process's virtual memory (e.g. VM's RAM is actually a contiguous range of qemu process's virtual address space). Hence guest physical addresses (GPAs) are mapped to a contiguous range of process's Host virtual addresses (HVAs). Linux host of course maintains a set of page tables to map the qemu process's virtual address space. So far so good.
From what said above, I believe the relevant qemu process's page tables can't be "reused" as EPT page tables, i.e. the latter are actually different pages/memory from host RAM allocated for that specific purpose.
Does the above make sense ? Thanks.
From Intel 64 SDM, it seems to me that EPT paging-structures (both 4-level and 5-level) are actually different from "standard" paging structures available in 32-bit protected mode and IA-32e mode (64 bit and compatibility submodes).
Hypervisor/VMM like qemu allocate guest physical memory to a VM from their process's virtual memory (e.g. VM's RAM is actually a contiguous range of qemu process's virtual address space). Hence guest physical addresses (GPAs) are mapped to a contiguous range of process's Host virtual addresses (HVAs). Linux host of course maintains a set of page tables to map the qemu process's virtual address space. So far so good.
From what said above, I believe the relevant qemu process's page tables can't be "reused" as EPT page tables, i.e. the latter are actually different pages/memory from host RAM allocated for that specific purpose.
Does the above make sense ? Thanks.