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    // read the BAR0 to BAR5 (Base Address Register 0 to 5)
    uint32_t bar0 = pci_read(bus, device, function, 0x10); // Read BAR0 (Base Address Register 0)
    uint32_t bar1 = pci_read(bus, device, function, 0x14); // Read BAR1 (Base Address Register 1)
    uint32_t bar2 = pci_read(bus, device, function, 0x18); // Read BAR2 (Base Address Register 2)
    uint32_t bar3 = pci_read(bus, device, function, 0x1C); // Read BAR3 (Base Address Register 3)
    uint32_t bar4 = pci_read(bus, device, function, 0x20); // Read BAR4 (Base Address Register 4)
    uint32_t bar5 = pci_read(bus, device, function, 0x24); // Read BAR5 (Base Address Register 5)
    // uint32_t bar6 = pci_read(bus, device, function, 0x28); // Read BAR6 (Base Address Register 6) // not present in all devices

    pci_device.base_address_registers[0] = bar0;           
    pci_device.base_address_registers[1] = bar1;
    pci_device.base_address_registers[2] = bar2;
    pci_device.base_address_registers[3] = bar3;
    pci_device.base_address_registers[4] = bar4;
    pci_device.base_address_registers[5] = bar5 & 0xFFFFFFF0;   // This is a pointer to the AHCI controller's memory address
    // pci_device.base_address_registers[6] = bar6; // Not used in this example
    

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uint32_t pci_read(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset) {
    uint32_t address = (1 << 31) | (bus << 16) | (device << 11) | (function << 8) | (offset & 0xFC);
    outl(CONFIG_ADDRESS, address);  // Write CONFIG_ADDRESS
    return inl(CONFIG_DATA);        // Read CONFIG_DATA     
}

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HBA_PORT_T* port = &abar->ports[0];

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void portRebase(HBA_MEM_T *abar, int port_no)
{
	HBA_PORT_T* port = &abar->ports[0];

	uint64_t phys = (uint64_t) abar;
	uint64_t virt = (uint64_t) phys_to_vir(phys);

	// map_virtual_memory(void *phys_addr, uint64_t virt_addr, size_t size, uint64_t flags);
	map_virtual_memory((void *)phys, virt, sizeof(HBA_MEM_T), (PAGE_WRITE | PAGE_PRESENT));

	uint32_t AHCI_BASE = (uint32_t) virt;


	stopCMD(port);	// Stop command engine
	
 
	// Command list offset: 1K * port_no
	// Command list entry size = 32
	// Command list entry maximum count = 32
	// Command list maximum size = 32 * 32 = 1K per port
	port->clb = AHCI_BASE + (port_no << 10);
	port->clbu = 0;
	memset((void*) (uint64_t) (port->clb), 0, 0x400);
 
	// FIS offset: 32K + 256 * port_no
	// FIS entry size = 256 bytes per port
	port->fb = AHCI_BASE + (32 << 10) + (port_no << 8);
	port->fbu = 0;
	memset((void*) (uint64_t) (port->fb), 0, 0x100);
 
	// Command table offset: 40K + 8K * port_no
	// Command table size = 256 * 32 = 8K per port
	HBA_CMD_HEADER_T* cmd_header = (HBA_CMD_HEADER_T*) (uint64_t) (port->clb);
	for (size_t i = 0; i < 32; i++)
	{
        // 8 prdt entries per command table
        // 256 bytes per command table, 64+16+48+16*8
		cmd_header[i].prdtl = 8;	
                                  
		// Command table offset: 40K + 8K*port_no + cmd_header_index*256
		cmd_header[i].ctba = AHCI_BASE + (40 << 10) + (port_no << 13) + (i << 8);
		cmd_header[i].ctbau = 0;
		memset((void*) (uint64_t) cmd_header[i].ctba, 0, 0x100);
	}
    // Start command engine
	startCMD(port);	
}
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