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I have decided to implement v86 mode into the kernel I have been writing.
I've been looking at how to do this, and something has been bugging me.

Suppose that the CPU is executing in v86 mode and hits an INT instruction/a hardware interrupt occurs.
When in v86 mode the stack is at SS:SP as in SS * 4 + SP.
In the interrupt handler the stack is at a totally different location based on the same SS:SP registers.

Is this right? Am I supposed to check whether the CPU was just executing v86 code and if it was flatten the stack address and fix the stack segment register?

(I'm not using paging/Don't know if that would matter here)

I highly suggest you read the Intel SDM or AMD APM for more details on this. I am using the AMD APM, and it describes in volume 2, chapter 8.8 exactly how that all works. In particular under what circumstances it invokes what handler in response to an interrupt in Virtual 8086 mode.

In this case, if it does invoke a protected-mode handler, it will read SS:ESP from the TSS even if the CPL is already 0. So there is no problem; the interrupt will be taken on the normal kernel stack.

nullplan wrote: ↑Fri Jan 17, 2025 3:14 pmeven if the CPL is already 0

The CPL can't be 0. Virtual 8086 mode always runs with CPL=3.

Thanks.

It depends on IOPL. Either you need to emulate all instructions that modify the interrupt flag, including the int instruction, or let the CPU emulate it.

Hardware interrupts are a different matter. In that case the CPU will load the kernel stack selector and save the V86 mode segment registers in addition to flags, cs and ip on this stack. Iret will then reload the v86 context including all the segment registers and pop of cs, ip, ss and sp. Exceptions work the same way as hardware interrupts.