How APIC Task Priority Register works
Posted: Tue Dec 10, 2024 5:52 pm
I am implementing an APIC timer and wiki says I should “Make sure the TPR (Task Priority Register) is set (so it won't block/postpone lower priority IRQs)”, I tried to find a description of TPR in Intel Manual but I was not able to do so(I would be glad if you could show me the location in the latest SDM).
I don't quite understand what value should be set for TPR, by default it is set to 0.
Also, I don't quite understand where the interrupt priority is specified, I guess it depends on the interrupt vector, the larger the vector the lower the priority, right?
I don't quite understand what value should be set for TPR, by default it is set to 0.
Also, I don't quite understand where the interrupt priority is specified, I guess it depends on the interrupt vector, the larger the vector the lower the priority, right?