Gap in understanding paging x86_64

[mrjbom]

I have a virtual address 0xffffa00001000000, it corresponds to a physical address 0x1000000.
This virtual address corresponds to the following indexes in the tables:
PML4[320]
PDPT[0]
PD[8]
PT[0]

I am trying to check this manually with QEMU.
Check PML4
PML4 = CR3 = 0x147c000
xp /1xg 0x147c000+(320*8)
000000000147ca00: 0x0000000001534023

Check PDPT
PDPT = 0x1534000
xp /1xg 0x1534000+(0*8)
0000000001534000: 0x0000000001535023

Check PD
PD = 0x1535000
xp /1xg 0x1535000+(8*8)
0000000001535040: 0x80000000010000a3

There's something wrong at this point, it's like I immediately looked up PT instead of PD. It can be seen that the physical address of the frame corresponding to the virtual address is written here.
Even if I try to interpret it as PT, I will get garbage.
xp /1xg 0x1000000+(0*8)
0000000001000000: 0x00010102464c457f

PML4 stores PDPT, PDPT stores PD, PD stores PT, doesn't it? Why is it that when I try to browse PD, I come straight to PT?

[MichaelPetch]

Check PD
PD = 0x1535000
xp /1xg 0x1535000+(8*8)
0000000001535040: 0x80000000010000a3

0x80000000010000a3 Bit 63-being set is the execute disable bit, bit 5 is accessed bit 0-1 and one are set so it is present and read write. The important thing is that bit 7 is set. This is the page size bit. When you reach a PD entry with the pagesize bit set (bit 7) you stop as you now have your physical address to a 2MiB page (you have to of course mask off the non address bits). If you find the page sizebit (bit 7) set in a PDPT entry you stop as you are dealing with the physical address of a 1GiB page.

[mrjbom]

Check PD
PD = 0x1535000
xp /1xg 0x1535000+(8*8)
0000000001535040: 0x80000000010000a3

When you reach a PD entry with the pagesize bit set (bit 7) you stop as you now have your physical address to a 2MiB page (you have to of course mask off the non address bits). If you find the page size bit set in a PDPT entry you stop as the you are dealing with the physical address of a 1GiB page.

If PS bit 1 is set in PD entry, PT is not used and the physical address contained in it is the 2 MB page address, right?

[MichaelPetch]

If PS bit 1 is set in PD entry, PT is not used and the physical address contained in it is the page address, right?

That is right. So in this case you have a 2MiB page mapped to physical address 0x0000000001000000. You do not continue down to the PT level as it doesn't apply.

[mrjbom]

If PS bit 1 is set in PD entry, PT is not used and the physical address contained in it is the page address, right?

That is right. So in this case you have a 2MiB page mapped to physical address 0x0000000001000000. You do not continue down to the PT level as it doesn't apply.

Great, thanks for the reply!