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There are three states of APIC:
Disabled, when apic_enable=0 and x2apic_enable=0.
xAPIC, when apic_enable=1 and x2apic_enable=0.
x2APIC, if both apic_enable=1 and x2apic_enable=1.
AMD claims that when a #RESET occurs, apic_base is set to 0xfee00000. However, what happens to this configuration after exiting BIOS? Will x2APIC be enabled automatically, and will the memory region at 0xfee00000 be reserved exclusively for APIC or potentially shared with other MMIO devices?

wishedtobe wrote: ↑Sat Sep 07, 2024 10:41 pm Will x2APIC be enabled automatically

The OS has to enable x2APIC mode by setting the 10th bit in the IA32_APIC_BASE MSR.

wishedtobe wrote: ↑Sat Sep 07, 2024 10:41 pm and will the memory region at 0xfee00000 be reserved exclusively for APIC or potentially shared with other MMIO devices?

Intel SDM Vol. 3A 11.4.5 (Relocating the Local APIC Registers) states that the starting address can be relocated from this address to solve conflicts with other memory maps meaning that it could be shared with other devices but BIOS/UEFI will most likely not map MMIO devices to this location.

wishedtobe wrote: ↑Sat Sep 07, 2024 10:41 pmWill x2APIC be enabled automatically, and will the memory region at 0xfee00000 be reserved exclusively for APIC or potentially shared with other MMIO devices?

For backwards compatibility, x2APIC will not be enabled by default. You should always use the MADT to find the local APIC's base address, but 0xFEE00000 is the only address I've ever seen.