Kernel development in NASM
Posted: Tue Sep 03, 2024 9:29 am
Hi everyone, I have a problem with interrupt management, below I insert the code.
It does not give errors but when calling a software interrupt (OX80) it does nothing.:
IDT.ASM:
IDT_SET_GATE:
IDT: db 256*16-1 dup(0)[/code]
macros that create the interrupt list:
thanks for the help.
It does not give errors but when calling a software interrupt (OX80) it does nothing.:
IDT.ASM:
Code: Select all
GLOBAL IDT_Build
IDT_Build:
pusha64
; Build the IDT
xor rdi, rdi ; create the 64-bit IDT (at linear address 0x0000000000000000)
mov rdi, IDT
mov rcx, 32 ; 32
mov rsi, isr_vector_asm ; ISR list
cld
make_exception_gates: ; make gates for exception handlers
mov rax, qword[rsi]
push rax ; save the exception gate to the stack for later use
stosw ; store the low word (15:0) of the address
mov ax, 0x0800
stosw ; store the segment selector
mov ax, 0x8F00
stosw ; store exception gate marker
pop rax ; get the exception gate back
shr rax, 16
stosw ; store the high word (31:16) of the address
shr rax, 16
stosd ; store the extra high dword (63:32) of the address.
xor rax, rax
stosd ; reserved
inc rsi ; next isr
;push rsi
;mov rsi, idt_install
;call debug_msg
;pop rsi
dec rcx
jnz make_exception_gates
mov rcx, 256-32
;mov rdi, IDT+32
;mov rsi, isr_vector_asm+32
make_interrupt_gates: ; make gates for exception handlers
mov rax, qword[rsi]
push rax ; save the exception gate to the stack for later use
stosw ; store the low word (15:0) of the address
mov ax, 0x0800
stosw ; store the segment selector
mov ax, 0x8E00
stosw ; store exception gate marker
pop rax ; get the exception gate back
shr rax, 16
stosw ; store the high word (31:16) of the address
shr rax, 16
stosd ; store the extra high dword (63:32) of the address.
xor rax, rax
stosd ; reserved
inc rsi ; next isr
;push rsi
;mov rsi, isr_install
;call debug_msg
;pop rsi
dec rcx
jnz make_interrupt_gates
; install the syscall handler
push rbx
xor rbx, rbx
mov rsi, ISR_Syscall
mov bx, 0x8F00
mov rax, 127
call IDT_Set_Gate
pop rbx
cli
lidt [IDTR]
sti
popa64
ret
Code: Select all
[code]IDT_Set_Gate:
push rax
push rdi
push rcx
push rbx
push rsi
mov rcx, rax ; save gate number
mov rax, 16 ; IDT address + gate number * 16
mul rcx
mov rdi, IDT
add rdi, rax ; set correct position inside the IDT
mov rax, rsi ; get the ISR address
push rax ; save the exception gate to the stack for later use
stosw ; store the low word (15:0) of the address
mov ax, 0x2800
stosw ; store the segment selector
mov ax, bx
stosw ; store exception gate marker
pop rax ; get the exception gate back
shr rax, 16
stosw ; store the high word (31:16) of the address
shr rax, 16
stosd ; store the extra high dword (63:32) of the address.
xor rax, rax
stosd ; reserved
mov rsi, gate
call debug_msg
pop rsi
pop rbx
pop rcx
pop rdi
pop rax
ret
SECTION .data
; The IDTR is the argument for the LIDT assembly instruction
; which loads the location of the IDT to the IDT Register.
;ALIGN 4
IDTR:
.Length dw 256*16-1 ; One less than the size of the IDT in bytes.
.Base dq IDT ; The linear address of the Interrupt Descriptor Table
; (not the physical address, paging applies).
macros that create the interrupt list:
Code: Select all
%macro ISR_ERR 1
ISR%1:
; error code is being pushed automatically by CPU (because "ERR")
push %1 ; push isr number
jmp isr_handler_asm
%endmacro
%macro ISR_NO_ERR 1
ISR%1:
push 0 ; push error code by hand as not automatically done by CPU (because "NO_ERR")
push %1 ; push isr number
jmp isr_handler_asm
%endmacro