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Hello,

I went back to OS developing after a long break, and I'm currently working on a little OS for fun. For context, the OS is meant to be booted on an EFI machine with x86_64. I've got my loader working, mapping the address space and everything and created a (currently empty) kernel that just sets up a GDT.

I recently decided to go back to my loader to add new features, especially those regarding ACPI and PCIe. I know that in order to easily find where the PCIe ECAM structure is located I have to first find the MCFG table in the ACPI tables. I did this and it works fine.

Now here are my two questions:

• When I enumerate the PCIe devices from the Host PCI Bridge (using QEMU by the way), I find a lot of devices, but no CPU is to be found... However, according to the PCI specification, there is a Base Class Code (0x0B) reserved for all kinds of processors. Is it normal I can't find the single CPU (not using SMP yet) running the QEMU VM in the PCIe devices?
  This is the list of devices I managed to enumerate: https://imgur.com/a/JSdw1Hs.

• The MCFG tables I'm working with right now only have one field (covering every bus in the PCI Segment Group 0), so I use the base address of this field as an absolute physical address as specified by the specification (recall this field covers bus 0). But what happens when I have more fields, especially with some covering only a part of the buses (let's say one from 0x00 to 0x7F and another one covering 0x80 to 0xFF). If I understood the specification correctly, the base address of the second field would be relative to the one contained in the field covering bus 0, is this right?
  What happens when more PCI Segment groups are present?
  
  To be more precise, this is what I don't understand: https://imgur.com/a/f0ID7nI.

Any help would be kindly appreciated, thanks in advance

onelastdevalex wrote: ↑Sat Aug 03, 2024 3:42 pm When I enumerate the PCIe devices from the Host PCI Bridge (using QEMU by the way), I find a lot of devices, but no CPU is to be found... However, according to the PCI specification, there is a Base Class Code (0x0B) reserved for all kinds of processors. Is it normal I can't find the single CPU (not using SMP yet) running the QEMU VM in the PCIe devices?

The CPU is not normally listed on PCI. There is a CPU class, and in theory this could be used for expansion cards with more CPUs on them, but I have not seen this in action. Most of the time, multiple CPUs are simply added to the system bus and the MADT.

onelastdevalex wrote: ↑Sat Aug 03, 2024 3:42 pm The MCFG tables I'm working with right now only have one field (covering every bus in the PCI Segment Group 0), so I use the base address of this field as an absolute physical address as specified by the specification (recall this field covers bus 0). But what happens when I have more fields, especially with some covering only a part of the buses (let's say one from 0x00 to 0x7F and another one covering 0x80 to 0xFF). If I understood the specification correctly, the base address of the second field would be relative to the one contained in the field covering bus 0, is this right?
What happens when more PCI Segment groups are present?

Segment groups are one level higher than busses. Both the case of segment groups exceeding 0 and the starting bus in the MCFG exceeding 1 are extremely rare. Honestly, I would put this under "cross this bridge when we come to it".

onelastdevalex wrote: ↑Sat Aug 03, 2024 3:42 pmIs it normal I can't find the single CPU (not using SMP yet) running the QEMU VM in the PCIe devices?

It's normal that you can't find any CPUs that way. CPUs aren't attached to each other using PCIe, so you won't see them when you enumerate PCIe.

onelastdevalex wrote: ↑Sat Aug 03, 2024 3:42 pmIf I understood the specification correctly, the base address of the second field would be relative to the one contained in the field covering bus 0, is this right?

The base address always points to where bus 0 would be, even if the start bus number is not 0. But the start bus number should always be 0, so you can just refuse to boot if you find a MCFG table where the start bus is not 0.

onelastdevalex wrote: ↑Sat Aug 03, 2024 3:42 pmWhat happens when more PCI Segment groups are present?

Segment groups are how you can have more than 256 buses in a single computer. Each segment group has a separate set of (up to) 256 buses, independent from the buses belonging to other segment groups.

Wow, everything is crystal clear now. Thank you both so much!