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Hello,

We are using SPI-1in Intel atom Elkhart lake, 0x6000

how to set the Idle state of MOSI line to high, right now its low, i.e before chip select is activated our device is expecting MOSI to be high

Note: Issue is with only idle state of MOSI, data is transmitted correctly

i tired googling this issue but unable to get right information

Thanks

ravi wrote:We are using SPI-1

Which one is that? There are several SPI controllers in there.

ravi wrote:how to set the Idle state of MOSI line to high, right now its low, i.e before chip select is activated our device is expecting MOSI to be high

Your device is broken. It should ignore MOSI before chip select is activated.

I looked at the SPI configuration registers, but I didn't see anything about setting the idle state of the MOSI line directly. However, the MOSI line is (probably) multiplexed with a GPIO, so you could use the GPIO to set MOSI high while you're not using SPI.

If that doesn't work (or you'd rather fix it in hardware), use an OR gate to combine chip select and MOSI.

hello Octocontrabass,

its PCH SPI-1(SIO-SPI-1) (GSPI Controller #1:- D30:F3 - 4B2Bh)

i also did not find the settings to do that,,, following are my observations

the same device works with other controller(i have matched all the CS/ CLK PO/PH, only thing that is different in the other controller(old black box kind of legacy stuff) is that the MOSI is high in the idle state and when CS is activated MOSI line transition to actual bits)

then i noticed, PCH SPI supports only Motorola format

i thought that MOSI should not matter data should be shifted in on the clock as per what is selected

Thanks
Ravi

ravi wrote:its PCH SPI-1(SIO-SPI-1) (GSPI Controller #1:- D30:F3 - 4B2Bh)

You should be able to use PAD_CFG_DW0_GPPC_B_22 to force MOSI high.

Thanks
Will try out bunch of other things along with this and let you guys know

Hello Octocontrabass

It was a HW problem we have fixed it, thanks for your help

i have more question, can PCH GSPI mentioned above be configured in 24_bit mode(i only saw 4, 8,16, 32)

Thanks
Ravi

Try setting SSCR0.EDSS to 1 and SSCR.DSS to 0b0111.

Hello Octocontrabass

i tried doing that before, but it was setting to 32,(may i would have pushed bits here and there,), i will check again

one more question

when i write data to spi bus in SSDR to transmit, and then immediately monitor status bit 4 in SSSR, it does not show immediately as SPI controller as busy its taking some time to show the SPI controller as busy.

can provide your suggestions

Thanks
Ravi

ravi wrote:when i write data to spi bus in SSDR to transmit, and then immediately monitor status bit 4 in SSSR, it does not show immediately as SPI controller as busy its taking some time to show the SPI controller as busy.

That sounds normal to me. It takes time for hardware to respond. You don't need to poll SSDR anyway, your driver should use interrupts.

Back on working on SPI

We are evaluating using interrupts(since it make our system less deterministic )


i trying DMA also, i had one more question regarding chip select

when i do a CS as software control, then how do get the accurate delay between CS going and SPI transmission(is manual delay function the only way)

Hello Octocontrabass

i wanted to try implement SPI with DMA, but i am not getting any good documentation for elkhart lake,, all i have is 1 paragraph of few lines in 636112,, which does not detail anything

for example as per early experience with DMA on ARM, i need to know the bus matrix and channel allocation, to understand the data flow from memory to peripheral(vice versa)

do you know from where to get this data

thanks
Ravi

ravi wrote:when i do a CS as software control, then how do get the accurate delay between CS going and SPI transmission(is manual delay function the only way)

The delays listed in the SSCR1.SPH description should occur whether CS is hardware or software controlled. If you need longer delays, you'll have to write your own delay function using a separate timer or counter.

ravi wrote:i wanted to try implement SPI with DMA, but i am not getting any good documentation for elkhart lake,, all i have is 1 paragraph of few lines in 636112,, which does not detail anything

GSPI DMA is similar to PSE DMA, so you can read section 22.23 to understand how GSPI DMA works.

Thanks

Hello Octocontrabass

i am not trying to get the clock right as per calculation

Intel 636112-1.7 section 18.3.4

gives 2 examples

2) if set SSCR0.SCR to 0 and set CLOCK REGs M =8190 and N =32760
i should get 25 MHZ clock,, but i am getting only 1MHZ,, i change the ratio as per calculation given then also its givening me 1 mhz

1) by setting M:N = 1 and SCR =3 i was expecting to get 25mhz,, but i seeing 200khz

clock gating is disabled(ie. set to Hw_clk) not sure how the f_input is 100Mhz,,, is standard?

Thanks
Ravi

It appears, is plug in my observed value w.r.t configured register value it appears f_input is 1Mhz,,,,not sure why


Thanks
Ravi