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Hello, I have 3 questions about how the BIOS configures AHCI controllers:

1. The wiki says “BIOS may have already configured all the necessary AHCI memory spaces. But the OS usually needs to reconfigure them to make them fit its requirements”. What are these ‘requirements’? As far as I can see, the BIOS can be fully trusted with its allocations (unless its buggy, but thats unlikely, isn’t it? AHCI is pretty crucial to boot the OS, if its installed on a SATA drive).
2. I’m assuming that these ‘memory spaces’ that the BIOS configures are the ABAR, the command lists and the received FISes. What about command tables? I mean, I’m assuming NOT because they are variable length (the PRDT can have different amounts of entries). I have to allocate my own command tables, correct?
3. When I allocate my command tables, do I need to set the memory region to uncached? I know AHCI uses DMA for data transfers, and so it participates in the cache coherency protocol, but does it use it for reading the command tables aswell?

ThisIsAnEpicUsername wrote:As far as I can see, the BIOS can be fully trusted with its allocations (unless its buggy, but thats unlikely, isn’t it? AHCI is pretty crucial to boot the OS, if its installed on a SATA drive).

It's actually very likely to be buggy. Firmware developers usually only check to make sure Windows can boot, so if Windows doesn't care that the firmware initialized something wrong, they won't bother to fix it.

ThisIsAnEpicUsername wrote:What about command tables?

The firmware probably did set some of those up, but like everything else, you shouldn't rely on them.

ThisIsAnEpicUsername wrote:When I allocate my command tables, do I need to set the memory region to uncached?

No. DMA is just a fancy name for when a device can read or write memory by itself instead of relying on the CPU to move data around.

Ok. I will reinitialise the controller and use new memory structures (except for the ABAR, because that is one thing that can be trusted, right?)

No. DMA is just a fancy name for when a device can read or write memory by itself instead of relying on the CPU to move data around.

So, basically all PCI MMIO that maps to some memory structure in RAM is accessed via DMA, and therefore doesn’t need to be set to uncached?

ThisIsAnEpicUsername wrote:(except for the ABAR, because that is one thing that can be trusted, right?)

Right.

ThisIsAnEpicUsername wrote:So, basically all PCI MMIO that maps to some memory structure in RAM is accessed via DMA, and therefore doesn’t need to be set to uncached?

Correct. RAM should always be set to WB.

Ok, thanks for the help.

Octocontrabass wrote:

ThisIsAnEpicUsername wrote:So, basically all PCI MMIO that maps to some memory structure in RAM is accessed via DMA, and therefore doesn’t need to be set to uncached?

Correct. RAM should always be set to WB.

Wait. RAM should always be set to WB, but MMIO regions aren't RAM. I don't think it is correct at all.

For example, a graphics framebuffer is an MMIO region and should not be WB (write-combining/WC is ok for a framebuffer in most cases).

I think the issue is that the premise of your question is wrong:

So, basically all PCI MMIO that maps to some memory structure in RAM is accessed via DMA

NOT correct. MMIO and DMA are two different ways of communicating with a device.