X86-64 paging global bit

[bmj]

How is the global bit used on 64 bit paging? Can it be used on the top level like when using 32 bit paging?

I am kind of confused by the images on the wiki for 6 for 64 4 bit paging. I'd don't know why there are two images, and what is meant with page-sized and non-page-sized.

Thanks

[thewrongchristian]

How is the global bit used on 64 bit paging? Can it be used on the top level like when using 32 bit paging?

The Global bit just prevents that page from being flushed from the TLB when the CR3 is updated. It's used for mappings that are shared between all address spaces, such as the kernel page mapping.

64-bit paging on x86 is just like PAE paging in 32-bit, except the "top" level is no longer 4 entries long, but the full 512 entries long (it also is no longer the top level either, but instead has possibly a 4th and 5th level above it.)

Global is a PTE bit, so if a higher level page table is mapping a large page (such as a 2MB page in PAE mode), then yes, it can have the Global bit set, and will be used across address spaces.

I am kind of confused by the images on the wiki for 6 for 64 4 bit paging. I'd don't know why there are two images, and what is meant with page-sized and non-page-sized.

Thanks

The PS field at the directory level indicates whether the physical address is:
- 0 - A pointer to the next level down page table.
- 1 - A pointer to an actual page, sized accordingly by the page table level.

For example, when PS=1 at the page directory level, the physical address is the address of a page of size 4MB (non-PAE) or 2MB (PAE). It's just discriminating between entries for big pages and entries for page tables.

[bmj]

How is the global bit used on 64 bit paging? Can it be used on the top level like when using 32 bit paging?

The Global bit just prevents that page from being flushed from the TLB when the CR3 is updated. It's used for mappings that are shared between all address spaces, such as the kernel page mapping.

64-bit paging on x86 is just like PAE paging in 32-bit, except the "top" level is no longer 4 entries long, but the full 512 entries long (it also is no longer the top level either, but instead has possibly a 4th and 5th level above it.)

Global is a PTE bit, so if a higher level page table is mapping a large page (such as a 2MB page in PAE mode), then yes, it can have the Global bit set, and will be used across address spaces.

I am kind of confused by the images on the wiki for 6 for 64 4 bit paging. I'd don't know why there are two images, and what is meant with page-sized and non-page-sized.

Thanks

The PS field at the directory level indicates whether the physical address is:
- 0 - A pointer to the next level down page table.
- 1 - A pointer to an actual page, sized accordingly by the page table level.

For example, when PS=1 at the page directory level, the physical address is the address of a page of size 4MB (non-PAE) or 2MB (PAE). It's just discriminating between entries for big pages and entries for page tables.