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Created a custom kernel that starts from UEFI and trying to get USB controller working,
but I never get any response to get device descriptor. On an old Intel MacBook the keyboard
and mouse are usb devices, two EHCI controllers with two and three companion UHCI
controllers respectively. I first tried writing my own code but got no response so then
tried adopting
https://github.com/pdoane/osdev/tree/master/usb
and the same problem again at
UsbDevInit in usb/dev.c

I was wondering how a controller can access memory that is not in memory mapped range.
It uses Bus Mastering PCI but I notice Linux and MacOS refer to DMA in their usb controller code.
What could be causing this problem?

burzin wrote:It uses Bus Mastering PCI but I notice Linux and MacOS refer to DMA in their usb controller code.

Bus mastering is one type of DMA.

burzin wrote:What could be causing this problem?

Does your PCI initialization code set up the command register in the configuration space? Firmware may not enable everything you need for you.

I eventually found the cause when I looked at the assembly output of clang compiler.
It was the compiler emitting quad instructions when it should have emitted long ones.
I replaced all the u32 typedefs with uint32_t and that fixed it.

Yes I do set up the PCI command register, that is very confusing. The ICH8 data sheet
says UHCI is hardwired to disable MMIO, I enable port io and bus mastering. Then
how does the controller access the frame list and buffers, but it works anyhow.

burzin wrote: Yes I do set up the PCI command register, that is very confusing. The ICH8 data sheet
says UHCI is hardwired to disable MMIO, I enable port io and bus mastering. Then
how does the controller access the frame list and buffers, but it works anyhow.

MMIO is mapping device registers into the memory address space. UHCI registers are defined in terms of IO port space, not memory mapped space (as indicated by PCI BAR0 bit 0).

The frame list is referenced by the Frame List Base Address register. That points to memory in the PCI device address space, which is access using PCI busmaster DMA. On PCs, that address space often corresponds to the same physical address space used by RAM memory, but it may not be so if the PCI device address space is mapped using an IOMMU.

The frame list itself points to queue heads (QH) and/or transfer descriptors (TD), which are the data structures which actually point to buffers, and again, those buffers are accessed using PCI busmaster DMA in the PCI device address space.

burzin wrote:Yes I do set up the PCI command register, that is very confusing. The ICH8 data sheet
says UHCI is hardwired to disable MMIO, I enable port io and bus mastering. Then
how does the controller access the frame list and buffers, but it works anyhow.

MMIO has nothing to do with how the PCI device accesses memory. MMIO is when the CPU uses memory instructions like MOV to access the PCI device's registers. Bus mastering DMA is when the PCI device accesses memory.

You can't access UHCI registers with MOV, so the MMIO bit does not need to be set.