OSDev.org

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// this functions expects a just resetted port to be present at address 0
void usb_register_device(usb_bus_t* bus)
{
    uint64_t addr = alloc_address(bus);

    // TODO: real hw hangs inside this function
    if(usb_set_address(bus, addr) != USB_TRANSFER_STATUS_OK)
        return;

    kernel_log("Done\n");

    // ....
}

usb_transfer_status_t usb_set_address(const usb_bus_t* bus, uint64_t addr)
{
    usb_request_packet_t setup;
    setup.type = USB_REQUEST_DIR_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD;
    setup.request = USB_REQUEST_SET_ADDRESS;
    setup.value = addr;
    setup.index = 0;
    setup.size = 0;

    return usb_transfer_control_out(bus, 0, 0, &setup);
}

usb_transfer_status_t usb_transfer_control_out(const usb_bus_t* bus, uint64_t addr, uint64_t endpoint, void* setup)
{
    usb_packet_t packets[2];
    memset(packets, 0, sizeof(usb_packet_t) * 2);

    packets[0].type = USB_PACKET_TYPE_SETUP;
    packets[0].maxlen = 8;
    packets[0].buffer = setup;
    
    packets[1].type = USB_PACKET_TYPE_IN;
    packets[1].maxlen = 0x800;
    packets[1].buffer = NULL;
    packets[1].toggle = 1;

    return uhci_transfer_packets(bus->hci.data, addr, endpoint, packets, 2);
}

usb_transfer_status_t transfer_packets(void* data, uint64_t addr, uint64_t endpoint, const usb_packet_t* packets, size_t num_packets)
{
    uhci_controller_t* controller = data;

    volatile alignas(0x20) transfer_descriptor_t tds[num_packets];
    for(size_t i = 0; i < num_packets; i++)
    {
        tds[i].link = i == num_packets - 1 ? TD_TERMINATE : ((uint32_t)(uint64_t)&tds[i + 1] | TD_DEPTH_FIRST);
        tds[i].flags = TD_STATUS_ACTIVE;

        if(i == num_packets - 1)
            tds[i].flags |= TD_IOC;

        if(port_status(controller, addr) == USB_PORT_STATUS_CONNECT_LOW_SPEED)
            tds[i].flags |= TD_LOW_SPEED;
        
        tds[i].maxlen = ((packets[i].maxlen ? packets[i].maxlen - 1 : 0) << 21) | (endpoint << 15) | (addr << 8);
        
        switch (packets[i].type)
        {
        case USB_PACKET_TYPE_SETUP: tds[i].maxlen |= TD_PID_SETUP; break;
        case USB_PACKET_TYPE_IN: tds[i].maxlen |= TD_PID_IN; break;
        case USB_PACKET_TYPE_OUT: tds[i].maxlen |= TD_PID_OUT; break;
        }

        if(packets[i].toggle)
            tds[i].maxlen |= TD_DATA_TOGGLE;

        tds[i].bufptr = (uint32_t)(uint64_t)packets[i].buffer;
    }

    volatile alignas(0x20) queue_head_t qh;
    qh.head_link = QH_TERMINATE;
    qh.element_link = (uint32_t)(uint64_t)&tds[0];

    for(uint32_t i = 0; i < 1024; ++i)
        controller->frame_list[i] = FRAMELIST_TERMINATE;
    controller->frame_list[0] = (uint32_t)(uint64_t)&qh | FRAMELIST_QH;

    sched_run(controller);

    while(!(inportw(controller->io + IO_USBSTS) & USBSTS_INT))
        asm("pause");

    sched_stop(controller);

    return USB_TRANSFER_STATUS_OK;
} 

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pci: enabled=1, chipset=i440fx
usb_uhci: enabled=1, port1=disk:"hd.img"

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bool reset_port(uhci_controller_t* controller, uint64_t port)
{
    if(port >= controller->num_ports)
        return false;
    uint16_t addr = controller->io + IO_PORTSC + port * 2;

    // issue port reset
    outportw(addr, inportw(addr) | PORTSC_PORT_RESET);
    pit_prepare_one_shot(50);
    pit_perform_one_shot();
    outportw(addr, inportw(addr) & ~PORTSC_PORT_RESET);

    // wait for port to be ready
    for(uint8_t i = 0; i < 10; i++)
    {
        pit_prepare_one_shot(10);
        pit_perform_one_shot();

        uint16_t status = inportw(addr);

        if(!(status & PORTSC_CONNECT_STATUS))
            break;

        if(status & (PORTSC_STATUS_CHANGE | PORTSC_ENABLE_CHANGE))
        {
            // clear status change
            outportw(addr, status | PORTSC_STATUS_CHANGE | PORTSC_ENABLE_CHANGE);
            continue;
        }

        if(status & PORTSC_ENABLE)
            return true;

        outportw(addr, status | PORTSC_ENABLE);
    }

    return false;
}

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config_interface: win32config

romimage: file=C:/bochs/bochs/bios/BIOS-bochs-latest

cpu: model=broadwell_ult
cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1
cpu: cpuid_limit_winnt=0

clock: sync=none, time0=local

memory: guest=512, host=512

vgaromimage: file=C:/bochs/bochs/bios/VGABIOS-lgpl-latest
vga: extension=vbe, update_freq=5, realtime=1, ddc=builtin

ata0: enabled=1, ioaddr1=0x1f0, ioaddr2=0x3f0, irq=14

ata0-master: type=disk, path="BonsOS.img", model="BonsOS.img", sect_size=512

boot: disk

log: log.txt

panic: action=ask
error: action=report
info: action=report
debug: action=ignore

mouse: enabled=0, type=imps2
private_colormap: enabled=0

pci: enabled=1, chipset=i440fx
magic_break: enabled=1

port_e9_hack: enabled=1

print_timestamps: enabled=0

com1: enabled=1, mode=file, dev=serial1.txt

usb_uhci: enabled=1, port1=disk:"..\FAT.IMG"

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bochs

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bochs -q

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  pci_write_word(pci->bus, pci->dev, pci->func, 0xC0, 0x8F00);

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while(!(inportw(controller->io + IO_USBSTS) & USBSTS_INT))
        asm("pause");