Invalid TSS exception of which I can't see the origin
Posted: Wed Oct 26, 2022 6:22 am
My problem is specifically with the context switching that must be done when an interrupt arrives in usermode: -d int indicates to me that a 0xa exception is happening.
Yet, I am certain that my TSS is well-formed, and that the ESP I'm providing is a correct address that is mapped as kernel's. Moreover, my interrupts handling is correctly called if I try to STI while still in kernel mode, which suggest that the problem comes exclusively from my TSS.
I really don't know from where this could come. Here is where I am setting up a TSS entry: https://github.com/thamugadi/mel/blob/main/gdt/gdt.c
Here is a dump of -d int -M smm=off : https://pastebin.com/PpA2irNP
I notice that it keeps jumping for no reason to 0xefb51 after the reset following the Invalid TSS exception.
Does anyone have any idea what's going on?
Yet, I am certain that my TSS is well-formed, and that the ESP I'm providing is a correct address that is mapped as kernel's. Moreover, my interrupts handling is correctly called if I try to STI while still in kernel mode, which suggest that the problem comes exclusively from my TSS.
I really don't know from where this could come. Here is where I am setting up a TSS entry: https://github.com/thamugadi/mel/blob/main/gdt/gdt.c
Here is a dump of -d int -M smm=off : https://pastebin.com/PpA2irNP
I notice that it keeps jumping for no reason to 0xefb51 after the reset following the Invalid TSS exception.
Does anyone have any idea what's going on?