Can MSIs target the IO APIC?

[pagnes]

I would say no. They are two different and independent mechanisms for interrupt delivery.

Then again, there's this sentence in the Intel SDM vol 3 explaining the Destination ID field of the MSI destination address range of the processor:

Destination ID — This field contains an 8-bit destination ID. It identifies the message’s target processor(s).
The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry if the IOAPIC is used to
dispatch the interrupt to the processor(s).

As far as I know, the MSI writes are handled by the root complex/host bridge in/and/or the system agent/UBox. Thus I don't see how the IO APIC gets into the picture. It's not even possible to make an MSI-capable device to write to an RTE of the IO APIC since the access to these is indexed.

It's theoretically possible for an SoC to have an MSI write in the standard processor range to be redirected through the IO APIC but I haven't found such capability in all the PCH datasheets, nor in a few Xeon datasheets, nor in the VT-d specification.

Note that I'm not asking if the IO APIC can deliver MSIs (it makes no sense to ask such). I'm asking about the meaning of the quoted sentence.

After some thinking, the only thing I came up with is that the sentence is to be interpreted as "If you are already using the IO APIC to dispatch interrupt, you can simply use the bits 63:56 of the relevant RTE to fill the Destination ID field of the MSI address".

I'm I missing some trivial link between MSIs and the IO APIC?

[Octocontrabass]

MSIs completely bypass the IOAPIC. That sentence is just poor editing on Intel's part.

[devc1]

MSI sends the interrupt directly to the target CPU, it has nothing to do with IOAPIC. You can send an IRQ 50 or IRQ 99 or whatever you want with MSI.

[pagnes]

MSI sends the interrupt directly to the target CPU, it has nothing to do with IOAPIC. You can send an IRQ 50 or IRQ 99 or whatever you want with MSI.

That's pretty obvious, as I already explained in the answer. The question was about what Intel wrote in their manual and if there was anything true in it. It was not about the pretty easy topic of MSIs themselves.

As already better answered by others, it's just poor editing.