LAPIC – problems with external interrupts - IA32

[mschoett]

Hi all,

I have problems processing external interrupts on application processors in an own IA32 multicore kernel (written in C/C++). LAPICs are not in x2APIC mode.

What works
[*] Bootstrapping of all application processors
[*] I can send a custom IPI to all cores -> interrupt processing works on all cores
[*] For external interrupts I have initialized the full redirection table of the IO-APIC (there is only one IO-APIC) to send interrupts using Fixed Mode to core0 (bootstrap processor)
[*] Afterwards the keyboard interrupt is enabled in the coressponding Redirection Table in the IO-APIC
[*] When I press a key then the interrupt is accepted by the LAPIC of core0 and everything works as expected in qemu and on real hardware, see attached figure

Problems
[*] I wanted to test handling of external interrupts on another core (not the bootstrap processor)
[*] I programmed the IO-APIC to use Delivery Mode Fixed with physical destination of an existing application core, e.g. core1
[*] I dump the state of several registers in an endless loop and I could verify that the interrupt is accepted by the LAPIC of core1 -> the correct bit is set in the Interrupt Request Register (IRR) of the LAPIC of core1; but the interrupt is never processed
[*] If I increase the Interrupt Priority Class of the Keyboard vector (from 2 to 3 or more) the interrupt is processed on an application core (in qemu and one some hardware but not all). I have an 8 core machine which does not even accept the interrupt (checked in IRR) with the same code working in qemu and on a dual core machine.

Checked things
[*] Everything works on core0
[*] All cores have the IE-Bit in EFLAGS set (interrupts should be accepted) -> checked

Priority should allow interrupt processing on all cores
[*] Task Priority Register (TPR) of all cores is set to 0,0 and checked
[*] Processor Priority (PR) is 0,0 on all cores, checked

No other interrupts are in service:
[*] All ISR-Bits of core1 LAPIC are and remain 0 -> there is no other interrupt in service while the keyboard interrupt is pending

LINT0 and LINT1 are disabled for all LAPICs

PIC is also disabled (done by bootstrap processor)

Questions
[*] Is this a model specific behaviour?
[*] According to the specification a TPR of 0,0 should allow interrupts of any priority
[*] Does anybody have an idea where to look from here?

Thank you very much for any hints!

Michael


Attached is a screenshot of how I test. I have a colored text window for each core where I can print status information.

[mschoett]

I continued to study code from other kernels (Linux, xv6, DragonFly) and tried to improve my code.

I am now able to process external interrupts from the keyboard on an application core (fixed addressing) without raising interrupt priority. The vector in the IOAPIC for the IOAPIC is set to 0x21. This works in qemu and an old dual core laptop (Thinkpad x60s).

However, another old laptop (also 2 cores) does not process the keyboard interrupts on the application core. An the 8 core machine (Intel i7-4770) also refuses to process external interrupts on any application core.

I played around with xv6 [1]. In qemu it works, like my code.

Today I installed xv6 on the 8 core machine and can boot it using grub2 (following the instructions here [2]) and xv6 has the same problem.

In ioapic.cc there is the function:

ioapiceanble(int irq, int cpunum)

Setting cpunum to 0 (bootstrap processor) works but setting cpunum to 1 (application processor) does not work.


[1]
https://github.com/mit-pdos/xv6-public

[2]
https://hoblovski.github.io/2019/03/16/ ... -grub.html

[bookman]

good problems, thanks