Need help: XHCI interrupter's pending bit not set

[longjin]

Hello!
I'm making an XHCI driver for my os, and I met a strange problem.
I send a ENABLE_SLOT command to the xhci host controller, and the interrupt target is 0, after the command been executed I receive an irq from the controller. When I'm dealing with the interrupt, I found that the pending bit in the 'interrupt management register' of XHCI interrupter0 is NOT set by the controller. The value of the register is '0x2', which means the interrupt enable bit is set but the pending bit is not set.
And, I don't clear the event handler busy bit in the dequeue register, then write a new ENABLE_SLOT command into the command ring. After the write, I found that the pending bit has been set, and the irq handler not run.

My question is: Why the pending bit is not set by the controller at the first time?

Thanks for your help!

[Octocontrabass]

Is there another device using the same interrupt vector?

Is the XHCI MMIO range mapped with an appropriate memory type?

[Demindiro]

You don't need to check the interrupter management register. You just need to check if the cycle bit is on (or off, see manual to find out when it needs to be on or off) of the TRB at current dequeue pointer/index.

Nitpick: note the -er in interrupter.

[Demindiro]

I didn't read your question properly, sorry for that (my fault for trying to answer a question in a haste).

I assume you're using MSI or MSI-X. In that case the IP is cleared automatically.

If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled, then the
assertion of the Interrupt Pending (IP) flag in Figure 4-22 generates a PCI Dword
write. The IP flag is automatically cleared by the completion of the PCI write.

So, from my understanding, how the IP flag works is:

• If IMODC == 0, then IP = 1
• If IP == 1, then generate interrupt and clear it immediately

So when you receive the first interrupt, the bit gets cleared.
When the second interrupt is generated (i.e. IP is set to 1) it stays at 1 because it can't generate an interrupt due to EHB not being cleared.

Also, this is why I think it's important to emphasize the -er in interrupter, as it is something that generates an interrupt. It is not something that represents an (active) interrupt.

[longjin]

I didn't read your question properly, sorry for that (my fault for trying to answer a question in a haste).

I assume you're using MSI or MSI-X. In that case the IP is cleared automatically.

If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled, then the
assertion of the Interrupt Pending (IP) flag in Figure 4-22 generates a PCI Dword
write. The IP flag is automatically cleared by the completion of the PCI write.

So, from my understanding, how the IP flag works is:

• If IMODC == 0, then IP = 1
• If IP == 1, then generate interrupt and clear it immediately

So when you receive the first interrupt, the bit gets cleared.
When the second interrupt is generated (i.e. IP is set to 1) it stays at 1 because it can't generate an interrupt due to EHB not being cleared.

Also, this is why I think it's important to emphasize the -er in interrupter, as it is something that generates an interrupt. It is not something that represents an (active) interrupt.

Thanks for your reply! The problem has solved. Thank u!!!