Switching from ring0 to ring3 cause GP
Posted: Fri Jun 17, 2022 1:13 pm
Hi everyone.
I'm trying to set up the correct ring0 -> ring3 switching, but I'm getting a General Protection exception because of that. Moreover, the all next instructions from ring3 are executed successfully.
this is my GDT:
When I'm in ring3 I check the CS register value (it contains 111b in the low bits), then I stop the execution (hlt, jmp ... hlt) and check the registers values
using qemu:
ES =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
CS =0008 0000000000000000 00000000 00209a00 DPL=0 CS64 [-R-]
SS =0000 0000000000000000 00000000 00000000
DS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
FS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
GS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
LDT=0000 0000000000000000 0000ffff 00008200 DPL=0 LDT
TR =0028 0000000000150ad8 00000068 0000e900 DPL=3 TSS64-avl
It's strange to me, why CS register value is 0x08, because the CS value check every time passes.
Also, I refer to the AMD system programming manual (vol 2). But I don't know yet, how to check the GP error code in my interrupt handler.
If anyone knows what I missed?
I appreciate any help
I'm trying to set up the correct ring0 -> ring3 switching, but I'm getting a General Protection exception because of that. Moreover, the all next instructions from ring3 are executed successfully.
this is my GDT:
Code: Select all
gdt64:
dq 0
.csd0:
dd 0
db 0
db 10011010b
db 10100000b
db 0x00
.dsd0:
dd 0
db 0
db 10010010b
db 10100000b
db 0x00
.csd3:
dd 0
db 0
db 11111010b
db 10100000b
db 0x00
.dsd3:
dd 0
db 0
db 11110010b
db 10100000b
db 0x00
.tss:
dw 0 ; limit
dw 0 ; base
db 0x00 ; base
db 11101001b
db 00000000b ; limit (4 bits)
db 0 ; base
dd 0
dd 0
using qemu:
ES =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
CS =0008 0000000000000000 00000000 00209a00 DPL=0 CS64 [-R-]
SS =0000 0000000000000000 00000000 00000000
DS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
FS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
GS =0023 0000000000000000 00000fff 00a0f300 DPL=3 DS [-WA]
LDT=0000 0000000000000000 0000ffff 00008200 DPL=0 LDT
TR =0028 0000000000150ad8 00000068 0000e900 DPL=3 TSS64-avl
It's strange to me, why CS register value is 0x08, because the CS value check every time passes.
Also, I refer to the AMD system programming manual (vol 2). But I don't know yet, how to check the GP error code in my interrupt handler.
If anyone knows what I missed?
I appreciate any help