PCI Configuration reads strange address for BAR0-BAR5
Posted: Fri Apr 15, 2022 9:38 am
Hiya all. Sorry for the frequent questions to this forum, but I have another problem. I've recently been trying to implement PCI.I've been going off the PCI page on the wiki for the configuration reading and interpretation. All seemed well, and I read a fairly rational looking list of devices, with notably one mass storage controller of type 0x6 (SATA, hopefully). However, once I tried reading the BAR* addresses for function 2 (or function 1, if you start counting at 0), I ran into a perplexing set of data. Here is the struct that my function produced (note that here, I only scanned for the base addresses of function 2 for now); Note that all numbers are in base 10:
This is strange, because the other devices read like this:
Granted, it may be nonsensical to scan for function 1 addresses for most devices, so I can understand why they would return 2³²-1. But why is the SATA device's address a (base 10) part of this number? This seems odd. Has anyone got an explanation for this?
As an aside, does anyone know any good resources for actual PCI communication? Do I just use the numbers returned as port numbers or memory addresses? Sorry if this is a stupid question or just something I overlooked on the wiki article?
Many thanks.
Code: Select all
PCIDevice {
bus: 0,
device: 1,
vendor_id: 32902,
device_id: 28672,
class: MassStorageController,
subclass_id: 6,
header_type: 0,
base_addresses_f1: Some(
[
0,
0,
0,
0,
49249,
0,
],
),
}
Code: Select all
PCIDevice {
bus: 0,
device: 2,
vendor_id: 4660,
device_id: 4369,
class: Unclassified,
subclass_id: 3,
header_type: 0,
base_addresses_f1: Some(
[
4294967295,
4294967295,
4294967295,
4294967295,
4294967295,
4294967295,
],
),
}
As an aside, does anyone know any good resources for actual PCI communication? Do I just use the numbers returned as port numbers or memory addresses? Sorry if this is a stupid question or just something I overlooked on the wiki article?
Many thanks.