Jumping into infinite loop when mapping virtual address
Posted: Mon Nov 15, 2021 7:12 pm
Like the title, i followed Jose's instructions on enabling paging. Everything was fine until it mapped the virtual address to the physical address above KMEM_MAX. At that point it fell into an infinite loop. I don't know how to fix this error, does anyone know how to fix it?
Here is my source code (copy from Jose, cause this is the only way I know to fix it, but useless):
In "paging.h":
In "paging.c":
When I use GDB to debug it, it will cause infinite loop in paging_init(): line "while(addr < PHYS_MAX) {"
When I can't use GDB for debugging, I use Qemu with the -no-shutdown -no-reboot -d int flag. It printed this:
Can anyone help me?
Here is my source code (copy from Jose, cause this is the only way I know to fix it, but useless):
In "paging.h":
Code: Select all
#ifndef PAGING_H
#define PAGING_H
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "../common/debug.h"
#include "../common/string.h"
#include "../interrupt/isr.h"
/** Assume 4KiB pages, not support any other sizes. */
#define PAGE_SIZE 4096
#define PTES_PER_PAGE 1024
#define PDES_PER_PAGE 1024
/** Number of physical frames available. Assume 128MiB physical memory. */
#define PHYS_MAX 0x08000000 /** 128MiB physical memory. */
#define NUM_FRAMES (PHYS_MAX / PAGE_SIZE)
/** Up to where is kernel memory, == the upper bound of kernel heap. */
#define KMEM_MAX 0x00800000 /** 8MiB reserved for the kernel. */
/**
* Page table entry format, 32bits per entry. Order in struct
* definition is from LSB -> MSB.
*
* See https://wiki.osdev.org/Paging for the detailed definition.
*/
struct page_table_entry {
uint32_t present : 1; /** Set -> present in memory. */
uint32_t writable : 1; /** Set -> user writable. (read/write bit) */
uint32_t user : 1; /** Set -> user accessible. */
uint32_t unused0 : 2; /** Unused 2 caching bits. */
uint32_t accessed : 1; /** Set -> accessed sinced mapped. */
uint32_t dirty : 1; /** Set -> page has been written to. */
uint32_t unused1 : 5; /** Unused 5 misc bits. */
uint32_t frame : 20; /** Physical frame number of the page. */
} __attribute__((packed));
typedef struct page_table_entry pte_t;
/**
* Page directory entry format, 32bits per entry. Order in struct
* definition is from LSB -> MSB.
*
* See https://wiki.osdev.org/Paging for the detailed definition.
*/
struct page_directory_entry {
uint32_t present : 1; /** Set -> present in memory. */
uint32_t writable : 1; /** Set -> user writable. (read/write bit) */
uint32_t user : 1; /** Set -> user accessible. */
uint32_t unused0 : 2; /** Unused 2 caching bits. */
uint32_t accessed : 1; /** Set -> accessed sinced mapped. */
uint32_t unused1 : 1; /** Unused bit. */
uint32_t size : 1; /** 0 -> using 4KiB page size. */
uint32_t unused2 : 4; /** Unused 4 misc bits. */
uint32_t frame : 20; /** Physical frame number of level-2 table. */
} __attribute__((packed));
typedef struct page_directory_entry pde_t;
/** Helper macros on addresses and page alignments. */
#define ADDR_PAGE_OFFSET(addr) ((addr) & 0x00000FFF)
#define ADDR_PAGE_NUMBER(addr) ((addr) >> 12)
#define ADDR_PDE_INDEX(addr) (ADDR_PAGE_NUMBER(addr) / 1024)
#define ADDR_PTE_INDEX(addr) (ADDR_PAGE_NUMBER(addr) % 1024)
#define ADDR_PAGE_ALIGNED(addr) (ADDR_PAGE_OFFSET(addr) == 0)
#define ADDR_PAGE_ROUND_DN(addr) ((addr) & 0xFFFFF000)
#define ADDR_PAGE_ROUND_UP(addr) (ADDR_PAGE_ROUND_DN((addr) + 0x00000FFF))
/** Helper macro on getting the pointed-to address stored in an entry. */
#define ENTRY_FRAME_ADDR(entry) ((uint32_t) (entry).frame << 12)
void paging_init();
void paging_switch_pgdir(pde_t *pgdir);
#endif
Code: Select all
#include "paging.h"
/** Kernel heap bottom address - should be above `elf_shstrtab_end`. */
uint32_t kheap_curr;
/**
* Auxiliary function for allocating (page-aligned) chunks of memory in the
* kernel heap region that never gets freed.
*
* Should only be used to allocate the kernel's page directory/tables and
* the frames bitmap and other things before our actual heap allocation
* algorithm setup.
*/
static uint32_t
_kalloc_temp(size_t size, bool page_align)
{
/** If `page_align` is set, return an aligned address. */
if (page_align && !ADDR_PAGE_ALIGNED(kheap_curr))
kheap_curr = ADDR_PAGE_ROUND_UP(kheap_curr);
/** If exceeds the 8MiB kernel memory boundary, panic. */
if (kheap_curr + size > KMEM_MAX)
error("_kalloc_temp: kernel memory exceeds boundary");
uint32_t temp = kheap_curr;
kheap_curr += size;
return temp;
}
/** Bitmap indicating free/used frames. */
static uint8_t *frame_bitmap;
/**
* Helper functions for managing free physical frames, using a bitmap
* data structure. Every bit indicates the free/used state of a corresponding
* physical frame. Frame number one-one maps to bit index.
*/
#define BITMAP_OUTER_IDX(frame_num) ((frame_num) / 8)
#define BITMAP_INNER_IDX(frame_num) ((frame_num) % 8)
/** Set a frame as used. */
static inline void
frame_bitmap_set(uint32_t frame_num)
{
size_t outer_idx = BITMAP_OUTER_IDX(frame_num);
size_t inner_idx = BITMAP_INNER_IDX(frame_num);
frame_bitmap[outer_idx] |= (1 << (7 - inner_idx));
}
/** Clear a frame as free. */
static inline void
frame_bitmap_clear(uint32_t frame_num)
{
size_t outer_idx = BITMAP_OUTER_IDX(frame_num);
size_t inner_idx = BITMAP_INNER_IDX(frame_num);
frame_bitmap[outer_idx] &= ~(1 << (7 - inner_idx));
}
/** Returns true if a frame is in use, otherwise false. */
static inline bool
frame_bitmap_check(uint32_t frame_num)
{
size_t outer_idx = BITMAP_OUTER_IDX(frame_num);
size_t inner_idx = BITMAP_INNER_IDX(frame_num);
return frame_bitmap[outer_idx] & (1 << (7 - inner_idx));
}
/**
* Allocate a frame and mark as used. Returns the frame number of
* the allocated frame, or panics if there is no free frame.
*/
static uint32_t
frame_bitmap_alloc(void)
{
for (size_t i = 0; i < (NUM_FRAMES / 8); ++i) {
if (frame_bitmap[i] == 0xFF)
continue;
for (size_t j = 0; j < 8; ++j) {
if ((frame_bitmap[i] & (1 << (7 - j))) == 0) {
/** Found a free frame. */
uint32_t frame_num = i * 8 + j;
frame_bitmap_set(frame_num);
return frame_num;
}
}
}
return NUM_FRAMES;
}
/**
* Walk a 2-level page table for a virtual address to locate its PTE.
* If `alloc` is true, then when a level-2 table is needed but not
* allocated yet, will perform the allocation.
*/
pte_t *
paging_walk_pgdir_at_boot(pde_t *pgdir, uint32_t vaddr, bool alloc)
{
size_t pde_idx = ADDR_PDE_INDEX(vaddr);
size_t pte_idx = ADDR_PTE_INDEX(vaddr);
/** If already has the level-2 table, return the correct PTE. */
if (pgdir[pde_idx].present != 0) {
pte_t *pgtab = (pte_t *) ENTRY_FRAME_ADDR(pgdir[pde_idx]);
return &pgtab[pte_idx];
}
/**
* Else, the level-2 table is not allocated yet. Do the allocation if
* the alloc argument is set, otherwise return a NULL.
*/
if (!alloc)
return NULL;
pte_t *pgtab = (pte_t *) _kalloc_temp(sizeof(pte_t) * PTES_PER_PAGE, true);
assert(pgtab != NULL);
memset(pgtab, 0, sizeof(pte_t) * PTES_PER_PAGE);
pgdir[pde_idx].present = 1;
pgdir[pde_idx].writable = 0;
pgdir[pde_idx].user = 1; /** Just allow user access on all PDEs. */
pgdir[pde_idx].frame = ADDR_PAGE_NUMBER((uint32_t) pgtab);
return &pgtab[pte_idx];
}
/** kernel's identity-mapping page directory. */
pde_t *kernel_pgdir; /** Allocated at paging init. */
/** Switch the current page directory to the given one. */
inline void
paging_switch_pgdir(pde_t *pgdir)
{
assert(pgdir != NULL);
asm volatile ( "movl %0, %%cr3" : : "r" (pgdir) );
}
/** Page fault (ISR # 14) handler. */
static void
page_fault_handler(interrupt_state_t *state)
{
/** The CR2 register holds the faulty address. */
uint32_t faulty_addr;
asm ( "movl %%cr2, %0" : "=r" (faulty_addr) : );
/**
* Analyze the least significant 3 bits of error code to see what
* triggered this page fault:
* - bit 0: page present -> 1, otherwise 0
* - bit 1: is a write operation -> 1, read -> 0
* - bit 2: is from user mode -> 1, kernel -> 0
*
* See https://wiki.osdev.org/Paging for more.
*/
bool present = state->err_code & 0x1;
bool write = state->err_code & 0x2;
bool user = state->err_code & 0x4;
/** Just prints an information message for now. */
info("Caught page fault {\n"
" faulty addr = %p\n"
" present: %d\n"
" write: %d\n"
" user: %d\n"
"}", faulty_addr, present, write, user);
panic("page fault not handled!");
}
/** Initialize paging and switch to use paging. */
void
paging_init(void)
{
/** Kernel heap starts above all ELF sections. */
kheap_curr = ADDR_PAGE_ROUND_UP((uint32_t) elf_shstrtab_end);
/**
* The frame bitmap also needs space, so allocate space for it in
* our kernel heap. Clear it to zeros.
*/
frame_bitmap = (uint8_t *) _kalloc_temp(NUM_FRAMES / 8, false);
memset(frame_bitmap, 0, NUM_FRAMES / 8);
/**
* Allocate the one-page space for the kernel's page directory in
* the kernel heap. All pages of page directory/tables must be
* page-aligned.
*/
kernel_pgdir = (pde_t *) _kalloc_temp(sizeof(pde_t) * PDES_PER_PAGE, true);
memset(kernel_pgdir, 0, sizeof(pde_t) * PDES_PER_PAGE);
/**
* Identity-map the kernel's virtual address space to the physical
* memory. This means we need to map all the allowed kernel physical
* frames (from 0 -> KMEM_MAX) as its identity virtual address in
* the kernel page table, and reserve this entire physical memory region.
*
* Assumes that `frame_bitmap_alloc()` behaves sequentially.
*/
uint32_t addr = 0;
while (addr < KMEM_MAX) {
uint32_t frame_num = frame_bitmap_alloc();
assert(frame_num < NUM_FRAMES);
pte_t *pte = paging_walk_pgdir_at_boot(kernel_pgdir, addr, true);
assert(pte != NULL);
/** Update the bits in this PTE. */
pte->present = 1;
pte->writable = 0; /** Has no affect. */
pte->user = 0;
pte->frame = frame_num;
addr += PAGE_SIZE;
}
/**
* Also map the rest of physical memory into the scheduler page table,
* so it could access any physical address directly.
*/
while (addr < PHYS_MAX) {
pte_t *pte = paging_walk_pgdir_at_boot(kernel_pgdir, addr, true);
assert(pte != NULL);
/** Update the bits in this PTE. */
pte->present = 1;
pte->writable = 0; /** Has no affect. */
pte->user = 0;
pte->frame = ADDR_PAGE_NUMBER(addr);
addr += PAGE_SIZE;
}
/**
* Register the page fault handler. This acation must be done before
* we do the acatual switch towards using paging.
*/
isr_register(INT_NO_PAGE_FAULT, &page_fault_handler);
// 14, add macro definition in `src/interrupt/isr.h`
/** Load the address of kernel page directory into CR3. */
paging_switch_pgdir(kernel_pgdir);
/**
* Enable paging by setting the two proper bits of CR0:
* - PG bit (31): enable paging
* - PE bit (0): enable protected mode
*
* We are not setting the WP bit, so the read/write bit of any PTE just
* controls whether the page is user writable - in kernel priviledge any
* page can be written.
*/
uint32_t cr0;
asm volatile ( "movl %%cr0, %0" : "=r" (cr0) : );
cr0 |= 0x80000001;
asm volatile ( "movl %0, %%cr0" : : "r" (cr0) );
}
When I can't use GDB for debugging, I use Qemu with the -no-shutdown -no-reboot -d int flag. It printed this:
Code: Select all
SMM: enter
EAX=00000001 EBX=00000000 ECX=02000000 EDX=02000628
ESI=0000000b EDI=02000000 EBP=000f2c72 ESP=00006d98
EIP=000ebaef EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000080 CCD=00000001 CCO=LOGICB
EFER=0000000000000000
SMM: after RSM
EAX=00000001 EBX=00000000 ECX=02000000 EDX=02000628
ESI=0000000b EDI=02000000 EBP=000f2c72 ESP=00006d98
EIP=000ebaef EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006dff
ESI=00006d3c EDI=07fbedc5 EBP=00006cfc ESP=00006cfc
EIP=00007bfb EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 008f9300
CS =f000 000f0000 ffffffff 008f9b00
SS =0000 00000000 ffffffff 008f9300
DS =0000 00000000 ffffffff 008f9300
FS =0000 00000000 ffffffff 008f9300
GS =0000 00000000 ffffffff 008f9300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=00006cfc CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006dff
ESI=00006d3c EDI=07fbedc5 EBP=00006cfc ESP=00006cfc
EIP=000f7bfc EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=07fabb00
ESI=000ea600 EDI=07fbedc5 EBP=00006cfc ESP=00006cfc
EIP=000f7c15 EFL=00000016 [----AP-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000014 CCD=00006ce8 CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=07fabb00
ESI=000ea600 EDI=07fbedc5 EBP=00006cfc ESP=00006cfc
EIP=00007c16 EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =0000 00000000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=00000001 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a22 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=00007bfb EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 008f9300
CS =f000 000f0000 ffffffff 008f9b00
SS =0000 00000000 ffffffff 008f9300
DS =0000 00000000 ffffffff 008f9300
FS =0000 00000000 ffffffff 008f9300
GS =ca00 000ca000 ffffffff 008f9300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=000069e2 CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a22 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=000f7bfc EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000005
ESI=00000000 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=000f7c15 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=000069ce CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000005
ESI=00000000 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=00007c16 EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=00000001 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a1c EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=00007bfb EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=000069dc CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a1c EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=000f7bfc EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000003
ESI=07f8cb00 EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=000f7c15 EFL=00000012 [----A--] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000010 CCD=000069c8 CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000003
ESI=07f8cb00 EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=00007c16 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000001 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a22 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=00007bfb EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=000069e2 CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a22 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=000f7bfc EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000005
ESI=00000000 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=000f7c15 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=000069ce CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000005
ESI=00000000 EDI=07fbedc5 EBP=000069e2 ESP=000069e2
EIP=00007c16 EFL=00000006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=00000001 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a1c EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=00007bfb EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=000069dc CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=000f7bfc ECX=00001234 EDX=00006aff
ESI=00006a1c EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=000f7bfc EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000000 CCO=EFLAGS
EFER=0000000000000000
SMM: enter
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000003
ESI=07eccb00 EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=000f7c15 EFL=00000012 [----A--] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
CS =0008 00000000 ffffffff 00c09b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
DS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
FS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
GS =0010 00000000 ffffffff 00c09300 DPL=0 DS [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6280 00000037
IDT= 000f62be 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000010 CCD=000069c8 CCO=EFLAGS
EFER=0000000000000000
SMM: after RSM
EAX=000000b5 EBX=00007c16 ECX=00005678 EDX=00000003
ESI=07eccb00 EDI=07fbedc5 EBP=000069dc ESP=000069dc
EIP=00007c16 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =db80 000db800 ffffffff 00809300
CS =f000 000f0000 ffffffff 00809b00
SS =0000 00000000 ffffffff 00809300
DS =0000 00000000 ffffffff 00809300
FS =0000 00000000 ffffffff 00809300
GS =ca00 000ca000 ffffffff 00809300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT= 00000000 00000000
IDT= 00000000 000003ff
CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000001 CCO=EFLAGS
EFER=0000000000000000