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[SOLVED] Physical address space mapped to MMIO
Posted: Fri Aug 13, 2021 5:31 am
by Rukog
In System Programming Guide, Part 1.pdf at 3.3 PHYSICAL ADDRESS SPACE I can read that
This physical address space can be mapped to read-write memory, read-only memory, and memory mapped I/O.
But I see nowhere where can I map MMIO on the physical address space.
Is this a GDT stuff right? but there is no option for that.
Re: Physical address space mapped to MMIO
Posted: Fri Aug 13, 2021 6:13 am
by nexos
MMIO appears no different to the CPU then other memory. The address translator takes care of it for you. I assume the Intel manual is being overly verbose here, as MMIO appears the same "read only" memory, or maybe "read / write" memory
Re: [SOLVED] Physical address space mapped to MMIO
Posted: Sat Aug 14, 2021 2:59 am
by davmac314
Rukog wrote:In System Programming Guide, Part 1.pdf at 3.3 PHYSICAL ADDRESS SPACE I can read that
This physical address space can be mapped to read-write memory, read-only memory, and memory mapped I/O.
But I see nowhere where can I map MMIO on the physical address space.
Is this a GDT stuff right? but there is no option for that.
No. It's not saying
you can map it. It's saying
it can be mapped.
That is, one a particular system, some particular physical address range might be for memory-mapped I/O. You can't control that range (or maybe you can, by tweaking knobs in the chipset, but that's getting off-topic). But you can't control it via the GDT or page tables.
The GDT is for segment descriptors which controls the mapping of an offset address to a linear address (which may be the same as a physical address, depending on whether paging is active).