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NASM structure and IDT question.
Posted: Fri Dec 02, 2005 12:00 am
by mrkaktus
I have such structure:
dw 0x0000 ; Offset 0-15
dw 0x08 ; Selector
db 00000000b ; null, Reserved
db 10001110b ; present , DPL0, 32bit
dw 0x0000 ; Offset 16-31
And I have pointer : ISR_0x20
So I have to put that pointer to fields Offset 0-15 and 16-31, but
I don't know how to do this in using NASM structures ;/.
I think that field Offset 0-15 I can just define as:
dw ISR_0x20
because I think NASM will put in this DW automatically cuted
data. But how to declare second field? I tried this:
dw ISR_0x20 >> 16
But NASM returns me that I can shift only scalars ;/.
Please help.
Re: NASM structure and IDT question.
Posted: Fri Dec 02, 2005 12:00 am
by JAAman
you cannot do this at compile time -- either hard-code it (my preference) or do it at runtime
Re: NASM structure and IDT question.
Posted: Sat Dec 03, 2005 12:00 am
by mrkaktus
So It will look messy ;/, I have done something like this:
mov eax, ISR_0x20
mov word [IDT_Tab + 32 * 8], ax
shr eax, 16
mov word [IDT_Tab + 32 * 8 + 6], ax
But doing something like this for every ISR won't look nice ;/. Maybe
I need to create from this some function that will get ISR adress and
number of field in IDT and I will call it for every ISR initialization, I
haven't got better idea ;/.
Re: NASM structure and IDT question.
Posted: Sat Dec 03, 2005 12:00 am
by Osbios
dw ISR_0x20 mod 0x10000 ; Offset 0-15
dw 0x08 ; Selector
db 00000000b ; null, Reserved
db 10001110b ; present , DPL0, 32bit
dw ISR_0x20 / 0x10000 ; Offset 16-31
The mod at the first Offset is importand for pointers over the 64 KiB mark. Some assemblers (e.g. fasm) dont cut the value but giving a error massage when the word value is over 64 Ki.
Re: NASM structure and IDT question.
Posted: Sat Dec 03, 2005 12:00 am
by mrkaktus
It doesn't work OsBios.
NASM didn't recognize MOD operand and I have error
message in second declaration:
"division operator may only be applied to scalar values"
(thesame like with using ">>" shift arguments).
So for a moment I'm using method that I write in my last post,
but there I have another problem, my ISR 0x20 (Sheduler)
runs only Once (i tested and the normal kernel code is running
fine all thet time - i use counter to test it). This is Shed code:
ISR_0x20:
pusha
push gs
push fs
push es
push ds
mov ebx, [ds:0x6F6]
inc ebx
mov [ds:0x6F6], ebx
mov si , temp
call DWORD_TO_DEC
mov ax, 5
mov bx, 5
mov si, temp
call PM_WRITE
pop ds
pop es
pop fs
pop gs
popa
iret
So, Sheduler executes once and shows "1" on screen and it is not
increasing ;/. I don't know what to do
.
(I put code after IRET but it wasn't executed so it returns normally).
And this is my PIT code:
mov al, 0x34 ;\_Wysylamy rozkaz zaprogramowania
out 0x43, al ;/ generatora 0, na tryb 2. (00110100b)
mov al, 156 ;\_Wysyla LSB (156)
out 0x40, al ;/
mov al, 46 ;\_Wysyla MSB (46)
out 0x40, al ;/ [ (46*256)+156=11932 - dzielnik zegara]
I'm setting it for 100Hz (99.998Hz).
Please help ;/.
Re: NASM structure and IDT question.
Posted: Sat Dec 03, 2005 12:00 am
by Osbios
Sorry, but I no longer use NASM so I forget that NASM handle modulo a bit different.
From the NASM Manual:
% and %% provide unsigned and signed modulo operators respectively.
NASM, like ANSI C, provides no guarantees about the sensible operation of the signed modulo operator.
Since the % character is used extensively by the macro preprocessor, you should ensure that both the signed and unsigned modulo operators are followed by white space wherever they appear.
Your code have no EOI, so put this stuff befor the POPs and IRET:
Code: Select all
mov al,0x20
out 0x20,al ;send EOI to the first PIC
On x86 systems the PICs always wait after a IRQ and sending no more IRQs until they get a EOI (end of interrupt) massage.
Re: NASM structure and IDT question.
Posted: Sat Dec 03, 2005 12:00 am
by mrkaktus
**** it was so easy and i was wondering what I have done wrong ;///
. Thanks a lot I will test it
.